Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - deserialisers LVTTL TSSOP 48

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FEATURES

D17

D18

GND

D19

D20

LVDSGND

A0M

A0P

A1M

A1P

LVDSV

LVDSGND

A2M

A2P

CLKINM

CLKINP

LVDSGND

PLLGND

PLLV

PLLGND

SHTDN

CLKOUT

D16

D15

D14

GND

D13

D12

D11

D10

GND

DGG PACKAGE

(TOP VIEW)

DESCRIPTION

SN65LVDS96

SLLS296H – MAY 1998 – REVISED JULY 2006

LVDS SERDES RECEIVER

• 3:21 Data Channel Compression at up to

1.428 Gigabits/s Throughput

• Suited for Point-to-Point Subsystem

Communication With Very Low EMI

• 3 Data Channels and Clock Low-Voltage

Differential Channels in and 21 Data and

Clock Low-Voltage TTL Channels Out

• Operates From a Single 3.3-V Supply and 250

mW (Typ)

• 5-V Tolerant SHTDN Input

• Rising Clock Edge Triggered Outputs

• Bus Pins Tolerate 4-kV HBM ESD

• Packaged in Thin Shrink Small-Outline

Package With 20 Mil Terminal Pitch

• Consumes <1 mW When Disabled

• Wide Phase-Lock Input Frequency Range

20 MHz to 68 MHz

• No External Components Required for PLL

• Inputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

• Industrial Temperature Qualified

= –40 ° C to 85 ° C

• Replacement for the DS90CR216

The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift

registers, a 7 × clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single

integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe

SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous

data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the

LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A

phase-locked loop clock synthesizer circuit generates a 7 × clock for internal clocking and an output clock for the

expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).

The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control.

The data bus appears the same at the input to the transmitter and output of the receiver with data transmission

transparent to the user(s). The only user intervention is the possible use of the shutdown/clear ( SHTDN)

active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on

this signal clears all internal registers to a low level.

The SN65LVDS96 is characterized for operation over ambient air temperatures of –40 ° C to 85 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 LVDS SERDES RECEIVER FEATURES • • • • • • • • • • • • • • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.
PAGE 2
SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM Serial-In/Parallel-Out Shift Register A0P Serial In A,B, ...G A0M CLK Serial-In/Parallel-Out Shift Register A1P Serial In A,B, ...G A1M CLK Serial-In/Parallel-Out Shift Register A2P Serial In A,B, ...
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SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 CLKIN Previous Cycle Current Cycle A0 Next Cycle D6 D5 D4 D3 D2 D1 D0 D6+1 D13 D12 D11 D10 D9 D8 D7 D13+1 D20 D19 D18 D17 D16 D15 D14 D20+1 D0-1 A1 D7-1 A2 D14-1 CLKOUT Dn Dn-1 Dn Dn+1 Figure 1.
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SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage range (2) –0.5 V to 4 V Voltage range at any terminal (except SHTDN) –0.5 V to VCC + 0.5 V Voltage range at SHTDN terminal Electrostatic discharge (3) –0.5 V to 5.
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SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VIT+ Positive-going differential Input voltage threshold VIT- Negative-going differential Input voltage threshold (2) VOH High-level output voltage IOH = –4 mA VOL Low-level output voltage IOH = 4 mA 0.
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SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION AP VID (VIAP + VIAM)/2 AM VIAP VIC VIAM Figure 2. Voltage Definitions COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE AND VCC 2.5 VIC – Common-Mode Input Voltage – V MAX at >3.15 V MAX at 3 V 2 1.5 1 0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|– Differential Input Voltage and VCC – V Figure 3.
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SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION (continued) tsu VOH 2.4 V D0–27 0.4 V VOL th VOH 2.4 V CLKOUT 0.4 V VOL Figure 5.
PAGE 8
SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION (continued) An Tektronix HFS9003/HFS9DG1 Stimulus System (Repeating Patterns 1110111 and 0001000) D0–D20 DUT CLKIN Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector CLKOUT NOTES: A. CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. B. The advance or delay is then reduced until there are no data errors observed. C.
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SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Reference + Σ Device Under Test VCO + Modulation v(t) = A sin(2πfmodt) HP8656B Signal Generator, 0.1 MHz–990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz–4200 MHz Modulation Input Device Under Test CLKIN Output CLKOUT DTS2070C Digital Time Scope Input Figure 7. Output Clock Jitter Test Setup CLKIN An ten SHTDN Dn Invalid Valid Figure 8.
PAGE 10
SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 TYPICAL CHARACTERISTICS WORST-CASE SUPPLY CURRENT vs FREQUENCY 120 I CC − Supply Current − mA 100 ÁÁ ÁÁ ÁÁ ÁÁ VCC = 3.6 V 80 VCC = 3 V 60 VCC = 3.3 V 40 20 0 30 40 50 60 f − Frequency − MHz Figure 10.
PAGE 11
SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 APPLICATION INFORMATION 16-BIT BUS EXTENSION In a 16-bit bus application (Figure 11), TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input.
PAGE 12
SN65LVDS96 www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS96DGGR Package Package Pins Type Drawing TSSOP DGG 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.8 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS96DGGR TSSOP DGG 48 2000 346.0 346.0 41.
PAGE 16
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.