Datasheet

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FEATURES APPLICATIONS

DESCRIPTION

SN65LVDT14 LOGIC DIAGRAM

(POSITIVE LOGIC)

SN65LVDT41 LOGIC DIAGRAM

(POSITIVE LOGIC)

SN65LVDT14

SN65LVDT41

SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006

MEMORY STICK™ INTERCONNECT EXTENDER CHIPSET WITH LVDS

SN65LVDT14—ONE DRIVER PLUS FOUR RECEIVERS

SN65LVDT41—FOUR DRIVERS PLUS ONE RECEIVER

• Memory Stick Interface Extensions With Long

• Integrated 110- Ω Nominal Receiver Line

Interconnects Between Host and Memory

Termination Resistor

Stick™

• Operates From a Single 3.3-V Supply

• Serial Peripheral Interface™ (SPI) Interface

• Greater Than 125 Mbps Data Rate

Extension to Allow Long Interconnects

• Flow-Through Pin-Out

Between Master and Slave

• LVTTL Compatible Logic I/Os

• MultiMediaCard™ Interface in SPI Mode

• General-Purpose Asymmetric Bidirectional

• ESD Protection On Bus Pins Exceeds 16 kV

Communication

• Meets or Exceeds the Requirements of

ANSI/TIA/EIA-644A Standard for LVDS

• 20-Pin PW Thin Shrink Small-Outline Package

With 26-Mil Terminal Pitch

The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. It is

designed to be used at the Memory Stick end of an LVDS based Memory Stick interface extension.

The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package.

It is designed to be used at the host end of an LVDS based Memory Stick interface extension.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Serial Peripheral Interface is a trademark of Motorola.

MultiMediaCard is a trademark of MultiMediaCard Association.

Memory Stick is a trademark of Sony.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 MEMORY STICK™ INTERCONNECT EXTENDER CHIPSET WITH LVDS SN65LVDT14—ONE DRIVER PLUS FOUR RECEIVERS SN65LVDT41—FOUR DRIVERS PLUS ONE RECEIVER FEATURES APPLICATIONS • • • • • • • • • Integrated 110-Ω Nominal Receiver Line Termination Resistor Operates From a Single 3.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3.3 3.6 VCC Supply voltage 3 VIH High-level input voltage 2 VIL Low-level input voltage |VID| Magnitude of differential input voltage VIC Common-mode input voltage, See Figure 1 TA Operating free-air temperature UNIT V V 0.1 V 0.8 V 0.6 V V ID 2 2.4 V ID 2 VCC - 0.8 V 85 °C -40 2.5 VIC − Common-Mode Input Voltage − V Max at VCC > 3.
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SN65LVDT14 SN65LVDT41 www.ti.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 DRIVER SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Differential output signal rise time tf Differential output signal fall time tsk(p) Pulse skew (|tPHL - tPLH|) Output tsk(pp) Part-to-part skew (2) NOM MAX 0.9 1.7 2.9 0.9 1.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 IOY Y II D IOZ VOD V VOY Z OY V OZ 2 VI VOC VOZ Figure 3. Driver Voltage and Current Definitions VID VIA CL 10 pF VIB VO VIA 1.4 V VIB 1V VID 0.4 V 0V –0.4 V tPHL VO tPLH VOH 80% VCC/2 20% VOL tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 49.9 Ω, ±1% (2 Places) 3V Y D Input VIA Z 2 pF 0V VOC VOC(PP) VOC(SS) VOC A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
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SN65LVDT14 SN65LVDT41 www.ti.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 50 Ω D Input 5Ω 10 kΩ 7V Y or Z Output 300 kΩ 7V TYPICAL CHARACTERISTICS RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 TA = 25°C, VCC = 3.3 V 3 2.5 2 1.5 1 0.5 0 −70 TA = 25°C, VCC = 3.3 V 4.5 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V 3.5 5 4 3.5 3 2.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 RECEIVER (continued) HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3 t PHL − High-To-Low Propagation Delay Time − ns t PLH − Low-To-High Propagation Delay Time − ns LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.9 VCC = 3 V 2.8 VCC = 3.3 V 2.7 2.6 VCC = 3.6 V 2.5 2.4 2.3 2.2 −50 −25 0 25 50 75 TA − Free-Air Temperature − °C 100 2.8 2.7 2.6 VCC = 3 V 2.5 VCC = 3.3 V 2.4 VCC = 3.6 V 2.3 2.
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SN65LVDT14 SN65LVDT41 www.ti.com SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 APPLICATION INFORMATION EXTENDING THE MEMORY STICK INTERFACE USING LVDS SIGNALING OVER DIFFERENTIAL TRANSMISSION CABLES SN65LVDT41 1D SCLK Memory BS Stick Host SDIO Controller DIR 2D 3D 4D SN65LVDT14 1Y SCLK 1Z 2Y BS 2Z 3Y DIR 3Z 4Y 5A 5R 1R 2A 2B 3A SCLK Memory BS Stick 2R SDIO 3R 3B SD1 4A 4R 4B 4Z CBT 1A 1B SD2 5B CBT 5Y 5D 5Z Figure 14.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Jan-2013 Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDT14PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN65LVDT41PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN65LVDT41PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDT14PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN65LVDT41PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN65LVDT41PWR TSSOP PW 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.