Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - receivers LVDS 0/4 SOIC 16 N

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FEATURES DESCRIPTION

APPLICATIONS

Timer

LVDT Device

Only

(One of Four Shown)

200

250

300

350

400

450

500

-60 -40 -20 0 20 40 60 80 100

Data Transfer Rate - Mxfr/s

DATA TRANSFER RATE

FREE-AIR TEMPERATURE

- Free-Air Temperature - °C

-1 prbs NRZ, V

= 0.4 V

= 1.2 V, C

= 5.5 pF, 40% Open Eye

4 Receivers Switching, Input Jitter < 45 ps

550

SN65LVDS352PW

SN65LVDS348PW

SN65LVDS348 , SN65LVDT348

SN65LVDS352 , SN65LVDT352

SLLS523E – FEBRUARY 2002 – REVISED MAY 2004

QUAD HIGH-SPEED DIFFERENTIAL RECEIVERS

• Meets or Exceeds the Requirements of ANSI

The SN65LVDS348, SN65LVDT348,

TIA/EIA-644A Standard

SN65LVDS352, and SN65LVDT352 are high-speed,

quadruple differential receivers with a wide

• Single-Channel Signaling Rates up to

common-mode input voltage range. This allows

560 Mbps

receipt of TIA/EIA-644 signals with up to 3-V of

• -4 V to 5 V Common-Mode Input Voltage

ground noise or a variety of differential and

Range

single-ended logic levels. The '348 is in a 16-pin

• Flow-Through Architecture

package to match the industry-standard footprint of

the DS90LV048. The '352 adds two additional V

• Active Failsafe Assures a High-level Output

and GND pins in a 24-pin package to provide higher

When an Input Signal Is not Present

data transfer rates with multiple receivers in

• SN65LVDS348 Provides a Wide Common-

operation. All offer a flow-through architecture with all

Mode Range Replacement for the

inputs on one side and outputs on the other to ease

SN65LVDS048A or the DS90LV048A

board layout and reduce crosstalk between

receivers. LVDT versions of both integrate a 110- Ω

line termination resistor.

• Logic Level Translator

These receivers also provide 3x the standard's

• Point-to-Point Baseband Data Transmission

minimum common-mode noise voltage tolerance.

Over 100- Ω Media

The -4 V to 5 V common-mode range allows usage

in harsh operating environments or accepts LVPECL,

• ECL/PECL-to-LVTTL Conversion

PECL, LVECL, ECL, CMOS, and LVCMOS levels

• Wireless Base Stations

without level shifting circuitry. See the Application

• Central Office or PABX Switches

Information Section for more details on the

ECL/PECL to LVDS interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 DESCRIPTION (CONTINUED) Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 1 pF 6.5 kΩ 60 kΩ Attenuation Network RIN+, A 250 kΩ RIN–, B 7V 7V 7V 110 Ω ’LVDT Only Attenuation Network VCC VCC 100 Ω 37 Ω EN, EN ROUT, Y 7V 4 Attenuation Network 7V 200 kΩ 3 pF 6.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2), VCC,VCCA,VCCD1, and VCCD2 -0.5 V TO 4 V Enables, ROUT, or Y Voltage range -0.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 2.5 4 6 ns tPHL Propagation delay time, high-to-low-level output 2.5 4 6 ns td1 Delay time, failsafe disable time td2 Delay time, failsafe enable time tsk(p) Pulse skew (|tpHL1 - tpLH1|) 0.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION (continued) 1000 Ω 100 Ω + 1000 Ω 100 Ω† VID + V1 V2 VO – – 10 pF VIC 10 pF 10 pF + – A. Remove for testing LVDT device. B. Input signal of 3 MHz, duty cycle of 50±0.2%, and transition time of < 1ns. C. Fixture capacitance ±20%. D.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 A or RIN+ Y or ROUT VID VIA or VRIN+ B or RIN– CL VOY or VROUT VIB or VRIN– A or VRIN+ 1.4 V B or VRIN– 1V >1.5 µs 0.4 V VID 0V –0.2 V –0.4 V tPHL tPLH td1 td2 VOH VOY or VROUT VCC/2 VOL tf A.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 1.2 V RIN– 500 Ω ROUT RIN+ Inputs EN VROUT + _ VTEST 10 pF EN VTEST 2.5 V VRIN+ 1V 2V 1.4 V 0.8 V 2V 1.4 V 0.8 V EN EN tPZL tPZL tPLZ tPLZ 2.5 V 1.4 V VOL +0.5 V VOL VROUT VTEST 0V 1.4 V VRIN+ 2V 1.4 V 0.8 V 2V 1.4 V 0.8 V EN EN tPZH tPZH VOH VOH –0.5 V 1.4 V 0V VROUT A.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 B 1.2 V 500 Ω Y A Inputs EN VO + _ VTEST 10 pF 2.5 V VTEST A 1V 2V 1.4 V 0.8 V EN tPZL tPLZ 2.5 V 1.4 V VOL +0.5 V VOL VO VTEST A 0V 1.4 V EN 2V 1.4 V 0.8 V tPZH tPHZ VOH VOH –0.5 V 1.4 V 0V VO A.
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SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 TYPICAL CHARACTERISTICS LOW-TO-HIGH PROPAGATION DELAY vs FREE-AIR TEMPERATURE HIGH-TO-LOWPROPAGATION DELAY vs FREE-AIR TEMPERATURE 5 5 See NO TAG 4.5 t PHL - High-to-Low Propagation Delay - ns t PLH - Low-to-High Propagation Delay - ns See NO TAG VCC = 3 V VCC = 3.3 V 4 VCC = 3.6 V 3.5 3 -50 0 50 VCC = 3 V 4.5 VCC = 3.3 V 4 VCC = 3.6 V 3.
PAGE 13
SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) DATA TRANSFER RATE vs FREE-AIR TEMPERATURE RMS SUPPLY CURRENT vs SWITCHING FREQUENCY 500 110 Maximum Transfer Rate - Mxfr/s 450 400 I CC - RMS Supply Current - mA 215 -1 prbs NRZ, VIC = 1.2 V, CL = 5.5 pF, 40% Open Eye, 4 Receivers Switching, VCC = 3.3 V, SN65LVDS348PW VID = 0.4 V 350 300 VID = 0.1 V VID = 0.
PAGE 14
SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 APPLICATION INFORMATION IMPEDANCE MATCHING AND REFLECTIONS A termination mismatch can result in reflections that degrade the signal at the load. A low source impedance causes the signal to alternate polarity at the load (oscillates) as shown in Figure 14. High source impedance results in the signal accumulating monotonically to the final value (stair step) as shown in Figure 15.
PAGE 15
SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 APPLICATION INFORMATION (continued) ACTIVE FAILSAFE FEATURE A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current LVDS failsafe solutions require either external components with subsequent reductions in signal quality or integrated solutions with limited application.
PAGE 16
SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 APPLICATION INFORMATION (continued) VCC R1 = 50 Ω R2 = 50 Ω ICC 5 Meters of CAT-5 LV/PECL R3 VEE R3 VB VCC ICC LVDS VB R1 R1 R2 R3 = 240 Ω Figure 17. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver DEVICE POWER AND GROUNDING The SN65LVDS352 device provides separate power and ground pins for the analog input section and the two digital output sections.
PAGE 17
SN65LVDS348 , SN65LVDT348 SN65LVDS352, SN65LVDT352 www.ti.com SLLS523E – FEBRUARY 2002 – REVISED MAY 2004 APPLICATION INFORMATION (continued) VCC VCCD1 Bypass Capacitor† DGND1 Bypass Capacitor† VCCA AGND VCCD2 Bypass Capacitor† DGND2 † Bypass capacitors used for data sheet electrical testing were low ESR ceramic, surface mount, 0.01 µF ±10%.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2009 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS348PWR Package Package Pins Type Drawing TSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDT348DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDT348PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS348PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDT348DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDT348PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDT352PWR TSSOP PW 24 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.