Datasheet

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FEATURES

PINOUT ASSIGNMENT

1 8

2 7

3 6

4 5

LVTTL

LVPECL

GND

APPLICATIONS

DESCRIPTION

SN65LVELT23

www.ti.com

......................................................................................................................................................... SLLS929A – JUNE 2009 – REVISED AUGUST 2009

3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

• Dual 3.3-V Differential LVPECL/LVDS to LVTTL

Buffer Translator

• 24-mA LVTTL Ouputs

• Operating Range

– PECL V

= 3 V to 3.6 V With

GND = 0 V

• Support for Clock Frequencies to >180 MHz

• 2-ns Typical Propagation Delay

• Internal Input Pullup and Pulldown Resistors

• Built-in Temperature Compensation

• Drop-In Compatible to MC100LVELT23

Table 1. PIN DESCRIPTION

• Data and Clock Transmission Over Backplane

PIN FUNCTION

• Signaling Level Conversion for Clock or Data

, D

PECL inputs

, Q

TTL outputs

Positive supply

The SN65LVELT23 is a low-power dual

GND Ground

LVPECL/LVDS to LVTTL translator device. The

device includes circuitry to maintain inputs at V

when left open. The SN65LVELT23 is housed in an

industry-standard SOIC-8 package and is also

available in a TSSOP-8 option.

ORDERING INFORMATION

(1)

PART NUMBER PART MARKING PACKAGE LEAD FINISH

SN65LVELT23D LVEL23 SOIC NiPdAu

SN65LVELT23DGK SIMI MSOP NiPdAu

(1) Devices with lead (Pb)-bearing terminals not initially available; contact TI sales representative for further information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (14 pages)

PAGE 1
SN65LVELT23 www.ti.com......................................................................................................................................................... SLLS929A – JUNE 2009 – REVISED AUGUST 2009 3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator FEATURES 1 • • • • • • • • Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator 24-mA LVTTL Ouputs Operating Range – PECL VCC = 3 V to 3.
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SN65LVELT23 SLLS929A – JUNE 2009 – REVISED AUGUST 2009......................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS PARAMETER CONDITION VALUE UNIT 3.8 V 0 to 3.
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SN65LVELT23 www.ti.com......................................................................................................................................................... SLLS929A – JUNE 2009 – REVISED AUGUST 2009 LVTTL OUTPUT DC CHARACTERISTICS (1) (VCC = 3.3 V; GND = 0 V) (2) PARAMETER IOS Output short-circuit current VOH Output high voltage (3) IOH = –3.0 mA VOL Output low voltage IOL = 24 mA (1) (2) (3) –40°C CONDITION 25°C MIN TYP MAX –120 –30 MIN 85°C TYP MAX –120 2.4 –30 2.
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SN65LVELT23 SLLS929A – JUNE 2009 – REVISED AUGUST 2009......................................................................................................................................................... www.ti.com Typical Output Loading Used for Device Evaluation Application TTL Receiver Characteristic Test RL *CL *CL Includes Fixture Capacitance AC TEST LOAD GND Figure 1. TTL Output Loading Used for Device Evaluation 2.0 V 0.8 V tr tf Figure 2. Output Rise and Fall Times IN IN 1.5 V 1.
PAGE 5
SN65LVELT23 www.ti.com......................................................................................................................................................... SLLS929A – JUNE 2009 – REVISED AUGUST 2009 OUTPUT VOLTAGE vs FREQUENCY 5 VCC = 3.3 V VOH @ TA = −40°C PO − Output Voltage − V 4 VOH @ TA = 25°C 3 VOH @ TA = 85°C 2 VOL @ TA = −40°C VOL @ TA = 25°C 1 VOL @ TA = 85°C 0 0 50 100 150 200 250 300 350 400 450 500 f − Frequency − MHz G001 Figure 5.
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SN65LVELT23 SLLS929A – JUNE 2009 – REVISED AUGUST 2009......................................................................................................................................................... www.ti.com REVISION HISTORY Changes from Revision Original (June 2009) to Revision A ......................................................................................... Page • 6 Changed MIN and MAX values for tPLH/tPHL in AC CHARACTERISTICS table.................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVELT23DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVELT23DR SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.