Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - transceivers LVDS, P2MP 8/8 TSSOP 64

www.ti.com

FEATURES

APPLICATIONS

DESCRIPTION

LOGIC DIAGRAM (POSITIVE LOGIC)

1DE

SN65MLVD080, SN65MLVD082

Channel 1

Channels 2 - 8

2DE - 8DE

2D - 8D

2R - 8R

2A - 8A

2B - 8B

SN65MLVD080

SN65MLVD082

SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005

8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

The M-LVDS standard defines two types of receivers,

designated as Type-1 and Type-2. Type-1 receivers

• Low-Voltage Differential 30- Ω to 55- Ω Line

(SN65MLVD080) have thresholds centered about

Drivers and Receivers for Signaling Rates

(1)

zero with 25 mV of hysteresis to prevent output

Up to 250 Mbps; Clock Frequencies Up to

oscillations with loss of input; Type-2 receivers

125 MHz

(SN65MLVD082) implement a failsafe by using an

• Meets or Exceeds the M-LVDS Standard

offset threshold. In addition, the driver rise and fall

times are between 1 and 2.0 ns, complying with the

TIA/EIA-899 for Multipoint Data Interchange

M-LVDS standard to provide operation at 250 Mbps

• Controlled Driver Output Voltage Transition

while also accommodating stubs on the bus. Receiver

Times for Improved Signal Quality

outputs are slew rate controlled to reduce EMI and

• –1 V to 3.4 V Common-Mode Voltage Range

crosstalk effects associated with large current surges.

Allows Data Transfer With 2 V of Ground

The M-LVDS standard allows for 32 nodes on the bus

Noise

providing a high-speed replacement for RS-485

where lower common-mode can be tolerated or when

• Bus Pins High Impedance When Driver

higher signaling rates are needed.

Disabled or V

≤ 1.5 V

The driver logic inputs and the receiver logic outputs

• Independent Enables for each Driver

are on separate pins rather than tied together as in

• Bus Pin ESD Protection Exceeds 8 kV

some transceiver designs. The drivers have separate

• Packaged in 64-Pin TSSOP (DGG)

enables (DE) and the receivers are enabled globally

through ( RE). This arrangement of separate logic

• M-LVDS Bus Power Up/Down Glitch Free

inputs, logic outputs, and enable pins allows for a

listen-while-talking operation. The devices are

characterized for operation from –40 ° C to 85 ° C.

• Parallel Multipoint Data and Clock

Transmission Via Backplanes and Cables

• Low-Power High-Speed Short-Reach

Alternative to TIA/EIA-485

• Cellular Base Stations

• Central-Office Switches

• Network Switches and Routers

The SN65MLVD080 and SN65MLVD082 provide

eight half-duplex transceivers for transmitting and

receiving Multipoint-Low-Voltage Differential Signals

in full compliance with the TIA/EIA-899 (M-LVDS)

standard, which are optimized to operate at signaling

rates up to 250 Mbps. The driver outputs have been

designed to support multipoint buses presenting

loads as low as 30- Ω and incorporates controlled

transition times to allow for stubs off of the backbone

transmission line.

(1) The signaling rate of a line, is the number of voltage

transitions that are made per second expressed in the units

bps (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS FEATURES • • • • • • • • • Low-Voltage Differential 30-Ω to 55-Ω Line Drivers and Receivers for Signaling Rates (1) Up to 250 Mbps; Clock Frequencies Up to 125 MHz Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange Controlled Driver Output Voltage Transition Times for Improved Signal Quality –1 V to 3.
PAGE 2
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage 2 3.3 VCC V VIL Low-level input voltage GND 0.8 V V Voltage at any bus terminal VA or VB –1.4 3.8 |VID| Magnitude of differential input voltage 0.
PAGE 4
SN65MLVD080 SN65MLVD082 www.ti.
PAGE 5
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 1 1.5 2.4 ns tpHL Propagation delay time, high-to-low-level output 1 1.5 2.
PAGE 6
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 2 4 6 ns tpHL Propagation delay time, high-to-low-level output 2 4 6 ns tr Output signal rise time 1 2.3 ns tf Output signal fall time 1 2.
PAGE 7
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION VCC IA A II D VAB IB VA B VI VOS VB VA + VB 2 Figure 1. Driver Voltage and Current Definitions 3.32 kΩ A + _ 49.9 Ω VAB D B -1 V ≤ Vtest ≤ 3.4 V 3.32 kΩ NOTE: All resistors are 1% tolerance. Figure 2. Differential Output Voltage Test Circuit R1 24.9 Ω A C1 1 pF D ≈ 1.3 V B ≈ 0.7 V VOS(PP) B C2 1 pF A R2 24.9 Ω VOS C3 2.5 pF ∆VOS(SS) VOS(SS) A.
PAGE 8
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) A D C1 1 pF C3 0.5 pF R1 Output 50 Ω B C2 1 pF VCC VCC/2 Input 0V tpLH tpHL VSS 0.9VSS VP(H) Output 0V VP(L) 0.1V SS 0 V SS tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ±5%. B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.
PAGE 9
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) A 0 V or VCC B VA or VB 1.62 kΩ , ±1% Figure 7.
PAGE 10
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 Table 1. Type-1 Receiver Input Threshold Test Voltages RESULTING DIFFERENTIAL INPUT VOLTAGE APPLIED VOLTAGES (1) RESULTING COMMONMODE INPUT VOLTAGE RECEIVER OUTPUT (1) VIA VIB VID VIC 2.400 0.000 2.400 1.200 0.000 2.400 –2.400 1.200 L 3.400 3.350 0.050 3.375 H 3.350 3.400 –0.050 3.375 L –1.350 –1.400 0.050 –1.375 H –1.400 –1.350 –0.050 –1.
PAGE 11
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 1.2 V RL 499 Ω B A Inputs CL RE VO + _ VTEST 15 pF VCC VTEST 1V A VCC RE VCC/2 0V tpZL tpLZ VCC VCC/2 VOL +0.5 V VOL VO VTEST 0V 1.4 V A VCC RE VCC/2 0V tpZH tpHZ VO VOH VOH -0.5 V VCC/2 0V A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B.
PAGE 12
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 INPUTS CLOCK INPUT VA -VB VA - VB VCM 0.2 V (’080) 1 V 0.4 V (’082) 1/f0 Period Jitter IDEAL OUTPUT VOH VA VCC/2 PRBS INPUT VOL 1/f0 VB VOH ACTUAL OUTPUT VCC/2 Peak to Peak Jitter VOH VOL OUTPUT V CC/2 tc(n) tjit(per) = tc(n) -1/f0 VOL tjit(pp) Cycle to Cycle Jitter VOH OUTPUT VCC/2 VOL tc(n) tc(n+1) tjit(cc) = | tc(n) - tc(n+1) | A.
PAGE 13
SN65MLVD080 SN65MLVD082 www.ti.
PAGE 14
SN65MLVD080 SN65MLVD082 www.ti.
PAGE 15
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY 180 VCC = 3.3 V TA = 25°C VCC = 3.3 V, TA = 25°C, f = 100 MHz 150 150 ICC − Supply Current − mA ICC − Supply Current − mA 180 SUPPLY CURRENT vs FREE-AIR TEMPERATURE Tx 120 Rx 90 60 120 Rx 90 60 30 30 0 10 30 50 70 90 f − Frequency − MHz 110 0 −50 130 −10 10 30 50 70 TA − Free-Air Temperature − °C Figure 14.
PAGE 16
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENTRACE LENGTH DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE 2.5 600 VCC = 3.3 V, TA = 25°C, f = 1 MHz, 550 Driver Propagation Delay − ns Differential Output Voltage − mV VCC = 3.3 V TA = 25°C 500 450 400 2 tPLH tPHL 1.5 1 0.5 350 0 −50 300 0 10 20 30 40 50 60 Trace Length − Inches 70 80 10 30 50 70 Figure 17.
PAGE 17
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) DRIVER TRANSITION TIME vs FREE-AIR TEMPERATURE TYPE-1 RECEIVER TRANSITION TIME vs FREE-AIR TEMPERATURE 2.1 2.5 VCC = 3.3 V, f = 1 MHz, TA = 25°C t r / tf − Rising/Falling Transition Time − ns t r / tf − Rising/Falling Transition Time − ns 2.5 tr 1.7 tf 1.3 0.9 0.5 −50 −30 −10 10 30 50 70 TA − Free-Air Temperature − °C tf 1.3 0.
PAGE 18
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) ADDED RECEIVER TYPE-2 PERIOD JITTER vs FREQUENCY ADDED DRIVER PERIOD JITTER vs FREQUENCY 18 VCC = 3.3 V Input = Clock VCC = 3.
PAGE 19
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) ADDED DRIVER CYCLE-TO-CYCLE JITTER vs FREQUENCY ADDED RECEIVER TYPE-1 DETERMINISTIC JITTER vs DATA RATE 350 VCC = 3.3 V Input = Clock Added Receiver Type-1 Deterministic Jitter − ps Added Driver Cycle-To-Cycle Jitter − ps 60 50 40 30 20 10 0 15 25 35 45 55 65 75 85 95 105 300 VCC = 3.
PAGE 20
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) ADDED RECEIVER TYPE-2 PEAK-TO-PEAK JITTER vs DATA RATE 120 450 VCC = 3.3 V, |VID| = 400 mV, VIC = 1 V Input = PRBS 215−1 360 Added Driver Peak-To-Peak Jitter − ps 270 180 90 100 80 60 40 20 0 50 70 90 110 130 150 0 30 170 190 210 70 90 110 130 150 170 190 210 Data Rate − Mbps Figure 33. Figure 34. DRIVER OUTPUT EYE PATTERN 200 Mbps, 215–1 PRBS, VCC = 3.
PAGE 21
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION Source Synchronous System Clock (SSSC) There are two approaches to transmit data in a synchronous system: centralized synchronous system clock (CSSC) and source synchronous system clock (SSSC). CSSC systems synchronize data transmission between different modules using a clock signal from a centralized source.
PAGE 22
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION (continued) tsk(o)Source = 2.0 ns – Output skew of data processing unit; any skew between data bits, or clock and data bits tsk(p-p)DRVR = 0.6 ns – Driver part-to-part skew of the SN65MLVD082 tsk(flight)BP = 0.4 ns – Skew of propagation delay on the backplane between data and clock tsk(p-p)RCVR = 1.
PAGE 23
SN65MLVD080 SN65MLVD082 www.ti.com SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION (continued) LIVE INSERTION/GLITCH-FREE POWER UP/DOWN The SN65MLVD080/082 family of products offered by Texas Instruments provides a glitch-free powerup/down feature that prevents the M-LVDS outputs of the device from turning on during a powerup or powerdown event.
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65MLVD080DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1 SN65MLVD082DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65MLVD080DGGR TSSOP DGG 64 2000 367.0 367.0 45.0 SN65MLVD082DGGR TSSOP DGG 64 2000 367.0 367.0 45.
PAGE 28
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 29
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.