Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers ATCA™ 250 Mbit/s TSSOP 48

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FEATURES

APPLICATIONS

LOGIC DIAGRAM

EN1

EN2

EN3

EN4

EN5

EN6

EN7

EN8

EN1

EN2

EN3

EN4

EN5

EN6

EN7

EN8

2 D

1 D

SN65MLVD128 SN65MLVD129

SN65MLVD128

SN65MLVD129

SLLS586 – MARCH 2004

1:8 LVTTL TO M-LVDS REPEATER DUAL 1:4 LVTTL TO M-LVDS REPEATER

• Bus Pins High Impedance When Disabled or

≤ 1.5 V

• LVTTL Receiver and Eight Line Drivers

Configured as an 8-Port M-LVDS Repeater – • Independent Enables for each Driver

SN65MLVD128

• Output-to-Ouput Skew t

sk(o)

≤ 160 ps

• 2 LVTTL Receivers and Eight Line Drivers Part-to-Part Skew t

sk(pp)

≤ 800 ps

Configured as Dual 4-Port M-LVDS Repeaters

• Single 3.3-V Voltage Supply

– SN65MLVD129

• Bus Pin ESD Protection Exceeds 9 kV

• Drivers Meet or Exceed the M-LVDS Standard

• Packaged in 48-Pin TSSOP (DGG)

(TIA/EIA-899)

• Low-Voltage Differential 30- Ω to 55- Ω Line

Drivers for Data Rates

(1)

Up to 250 Mbps or

• AdvancedTCA™ ( ATCA™) Clock Bus Driver

Clock Frequencies Up to 125 MHz

• Clock Distribution

• Power Up/Down Glitch Free

• Data and Clock Repeating Over Backplanes

• Controlled Driver Output Voltage Transition

and Cables

Times for Improved Signal Quality

• Cellular Base Stations

(1) The data rate of a line, is the number of voltage transitions

• Central Office Switches

that are made per second expressed in the units bps (bits per

• Network Switches and Routers

second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

AdvancedTCA, ATCA are trademarks of PCI Industrial Computer Manufacturers Group.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

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SN65MLVD128 SN65MLVD129 www.ti.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M-LVDS translators/repeaters. Outputs comply with the M-LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to 125 MHz.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 RECOMMENDED OPERATING CONDITIONS MIN NOM 3.3 MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage (1) 2 VCC V VIL Low-level input voltage (2) 0 0.8 V –1.4 3.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX UNIT LVTTL (D, EN) INPUT SPECIFICATIONS |IIH| High-level input current VIH = 2 V or VCC |IIL| Low-level input current VIL = GND or 0.8 V Ci Input capacitance VI = 0.4 sin(30E6πt) + 0.
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SN65MLVD128 SN65MLVD129 www.ti.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 PARAMETER MEASUREMENT INFORMATION VCC IA A II VA + VB D 2 VAB IB VY B VI VOS VB Figure 1. Driver Voltage and Current Definitions 3.32 kΩ A + _ 49.9 Ω VAB D B -1 V ≤ Vtest ≤ 3.4 V 3.32 kΩ NOTE: All resistors are 1% tolerance. Figure 2. Differential Output Voltage Test Circuit R1 24.9 Ω A C1 1 pF D ≈ 1.3 V B ≈ 0.7 V VOS(PP) B C2 1 pF A R2 24.9 Ω VOS C3 2.5 pF ∆VOS(SS) VOS(SS) A.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC/2 Input 0V tpLH tpHL VSS 0.9VSS VP(H) Output 0V VP(L) 0.1V SS 0 V SS tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal R1 24.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 PARAMETER MEASUREMENT INFORMATION (continued) VCC CLOCK INPUT VCC/2 0V 1/f0 Period Jitter IDEAL OUTPUT 0 V VA -VB VCC PRBS INPUT 0V ACTUAL OUTPUT 0 V VA -VB VCC/2 1/f0 Peak to Peak Jitter VA -VB tc(n) tjit(per) = tc(n) -1/f0 OUTPUT 0 V VA -VB tjit(pp) Cycle to Cycle Jitter OUTPUT 0V VA - VB tc(n) tc(n+1) tjit(cc) = | tc(n) - tc(n+1) | A. All input pulses are supplied by an Agilent 8304A Stimulus System. B.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 Table 1. Terminal Functions PIN NAME TYPE NO.
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SN65MLVD128 SN65MLVD129 www.ti.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL OUTPUT VOLTAGE MAGNITUDE vs INPUT FREQUENCY PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 650 2.4 TA = 25 C EN = VCC RL = 50 , 2.3 t pd − Propagation Delay Time − ns VAB − Differential Output Voltage Magnitude − mV 700 600 VCC = 3.6 V VCC = 3.3 V 550 VCC = 3 V 500 VCC = 3.3 V f = 500 kHz EN = VCC RL = 50 2.2 2.1 tPLH 2 1.9 1.8 tPHL 1.7 450 25 50 75 100 1.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 TYPICAL CHARACTERISTICS (continued) PERIOD JITTER vs CLOCK FREQUENCY CYCLE-TO-CYCLE JITTER vs CLOCK FREQUENCY 13 1.0 t jit(per) − Period Jitter − ps 0.8 12 t jit(c-c) − Cycle-To-Cycle Jitter − ps 0.9 VCC = 3.3 V, TA = 25 C, Input = Clock All EN = VCC See Figure 8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 11 10 9 8 7 6 5 4 3 2 1 0 0 25 50 75 100 f − Clock Frequency − MHz 125 25 50 75 100 f − Clock Frequency − MHz Figure 15. 12 VCC = 3.
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SN65MLVD128 SN65MLVD129 www.ti.com SLLS586 – MARCH 2004 APPLICATION INFORMATION CLOCK DISTRIBUTION SN65MLVD128 Output SN65MLVD128 Output Input Source: 19.6608 MHz Clock With 50% Duty Cycle, VCC = 3.3 V, RL = 50 , CL = 2.5 pF Input Source: 61.44 MHz Clock With 50% Duty Cycle, VCC = 3.3 V, RL = 50 , CL = 2.5 pF Output duty cycle = 50.01%. Vertical scale = 142 mV/div Horizontal scale = 4 ns/div Output Duty cycle = 49.97%. Vertical scale = 142 mV/div Horizontal scale = 11 ns/div Figure 17.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65MLVD128DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN65MLVD129DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65MLVD128DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN65MLVD129DGGR TSSOP DGG 48 2000 346.0 346.0 41.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.