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FEATURES DESCRIPTION

APPLICATIONS

SN65MLVD200A , SN65MLVD202A

SN65MLVD204A , SN65MLVD205A

SLLS573 – DECEMBER 2003

MULTIPOINT-LVDS LINE DRIVER AND RECEIVER

• Low-Voltage Differential 30- Ω to 55- Ω Line

The SN65MLVD200A, 202A, 204A, and 205A are

Drivers and Receivers for Signaling Rates

(1)

multipoint-low-voltage differential (M-LVDS) line

Up to 100 Mbps, Clock Frequencies up to

drivers and receivers, which are optimized to operate

at signaling rates up to 100 Mbps. All parts comply

50 MHz

with the multipoint low-voltage differential signaling

• Type-1 Receivers Incorporate 25 mV of

(M-LVDS) standard TIA/EIA-899. These circuits are

Hysteresis (200A, 202A)

similar to their TIA/EIA-644 standard compliant LVDS

• Type-2 Receivers Provide an Offset(100 mV)

counterparts, with added features to address

Threshold to Detect Open-Circuit and Idle-Bus

multipoint applications. The driver output has been

Conditions (204A, 205A)

designed to support multipoint buses presenting

loads as low as 30 Ω , and incorporates controlled

• Meets or Exceeds the M-LVDS Standard

transition times to allow for stubs off of the backbone

TIA/EIA-899 for Multipoint Data Interchange

transmission line.

• Power Up/Down Glitch Free

These devices have Type-1 and Type-2 receivers

• Controlled Driver Output Voltage Transition

that detect the bus state with as little as 50 mV of

Times for Improved Signal Quality

differential input voltage over a common-mode

• –1 V to 3.4 V Common-Mode Voltage Range

voltage range of –1 V to 3.4 V. The Type-1 receivers

Allows Data Transfer With 2 V of Ground

exhibit 25 mV of differential input voltage hysteresis

Noise

to prevent output oscillations with slowly changing

signals or loss of input. Type-2 receivers include an

• Bus Pins High Impedance When Disabled or

offset threshold to provide a known output state

≤ 1.5 V

under open-circuit, idle-bus, and other fault

• 200-Mbps Devices Available (SN65MLVD201,

conditions.

203, 206, 207)

The SN65MLVD200A, 202A, 204A, and 205A have

• Bus Pin ESD Protection Exceeds 8 kV

enhancements over their predecessors. Improved

• Package in 8-Pin SOIC (200A, 204A) and

features include better controlled slew rate on the

14-Pin SOIC (202A, 205A)

driver output to help minimize reflections while

improving overall signal integrity (SI) resulting in

• Improved Alternatives to the SN65MLVD200,

better jitter performance. Additionally, 8-kV ESD

202, 204, and 205

protection on the bus pins for more robustness. The

same footprint definition was maintained making for

an easy drop-in replacement for a system

• Low-Power High-Speed Short-Reach

performance upgrade.

Alternative to TIA/EIA-485

The devices are characterized for operation from

• Backplane or Cabled Multipoint Data and

–40 ° C to 85 ° C.

Clock Transmission

• Cellular Base Stations

• Central-Office Switches

• Network Switches and Routers

(1) The signaling rate of a line, is the number of voltage

transitions that are made per second expressed in the nits

bps (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 RECOMMENDED OPERATING CONDITIONS MIN NOM 3.3 MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V V Voltage at any bus terminal VA, VB, VY or VZ –1.4 3.8 |VID| Magnitude of differential input voltage 0.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 2 2.5 3.5 ns tpHL Propagation delay time, high-to-low-level output 2 2.5 3.5 ns tr Differential output signal rise time 2 2.6 3.2 ns tf Differential output signal fall time 2 2.6 3.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC IA or IY A/Y II D IB or IZ VAB or VYZ VA or VY B/Z VI VOS VB or VZ VA + VB 2 or VY + VZ 2 Figure 1. Driver Voltage and Current Definitions 3.32 kΩ A/Y VAB or VYZ D B/Z A. + _ 49.9 Ω -1 V ≤ Vtest ≤ 3.4 V 3.32 kΩ All resistors are 1% tolerance. Figure 2. Differential Output Voltage Test Circuit R1 24.9 Ω A/Y C1 1 pF D ≈ 1.3 V B/Z ≈ 0.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION (continued) A/Y D C1 1 pF C3 0.5 pF R1 Output 50 Ω B/Z C2 1 pF VCC VCC/2 Input 0V tpLH tpHL VSS 0.9VSS VP(H) Output 0V VP(L) 0.1V SS 0 V SS tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION (continued) A/Y 0 V or VCC B/Z VA, VB, VY or VZ 1.62 kΩ , ±1% Figure 7. Maximum Steady State Output Voltage VCC CLOCK INPUT VCC/2 0V 1/f0 Period Jitter IDEAL OUTPUT 0 V VA -VB or VY -VZ VCC PRBS INPUT 0V ACTUAL OUTPUT 0 V VA -VB or VY -VZ VCC/2 1/f0 Peak to Peak Jitter VA -VB or VY -VZ OUTPUT 0 V Diff tc(n) tjit(per) = tc(n) -1/f0 VA -VB or VY -VZ tjit(pp) A.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 Table 1. Type-1 Receiver Input Threshold Test Voltages RESULTING DIFFERENTIAL INPUT VOLTAGE APPLIED VOLTAGES (1) RESULTING COMMONMODE INPUT VOLTAGE RECEIVER (1)OUTPUT VIA VIB VID VIC 2.400 0.000 2.400 1.200 0.000 2.400 –2.400 1.200 L 3.425 3.335 0.050 3.4 H 3.375 3.425 –0.050 3.4 L –0.975 –1.025 0.050 –1 H –1.025 –0.975 –0.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 1.2 V B RL 499 Ω R A Inputs CL RE + _ VO VTEST 15 pF VCC VTEST 1V A VCC RE VCC/2 0V tpZL Output tpLZ VCC VCC/2 VOL +0.5 V VOL R VTEST 0V 1.4 V A VCC RE VCC/2 0V tpZH tpHZ VO VOH VOH -0.5 V VCC/2 0V A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 INPUTS VA -VB 0.2 V - Type 1 0.4 V - Type 2 CLOCK INPUT VA -VB 1/f0 VIC 1V Period Jitter IDEAL OUTPUT VOH VA VCC/2 PRBS INPUT VOL 1/f0 VB VOH ACTUAL OUTPUT VCC/2 Peak to Peak Jitter VOH VOL tc(n) tjit(per) = tc(n) -1/f0 OUTPUT V CC/2 VOL tjit(pp) A. All input pulses are supplied by an Agilent 8304A Stimulus System. B.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 30 20 ICC − Supply Current − mA Tx ICC − Supply Current − mA VCC = 3.3 V f = 50 MHz VID = 200 mV VIC = 1 V 25 15 10 Rx VCC = 3.3 V VID = 200 mV VIC = 1 V TA = 25°C 5 20 Tx 15 10 Rx 5 0 0 10 20 30 40 50 −40 f − Frequency − MHz Figure 14.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE RECEIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE 2.8 4 Receiver Propagation Delay − ns Driver Propagation Delay − ns VCC = 3.3 V f = 1 MHz RL = 50 Ω 2.6 tpHL 2.4 tpLH 2.2 2 VCC = 3.3 V VID = 200 mV VIC = 1 V f = 1 MHz CL = 15 pF 3.80 3.60 tpLH 3.40 3.20 3 −40 −15 10 35 60 −40 85 10 35 60 Figure 17.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) ADDED DRIVER PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE ADDED RECEIVER CYCLE-TO-CYCLE JITTER vs CLOCK FREQUENCY 72 40 VCC = 3.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) Vertical Scale = 127.2 mV/div SN65MLVD200A DRIVER OUTPUT EYE PATTERN vs 100 Mbps, 215-1 PRBS, RL = 50 Ω Horizontal Scale = 2 ns/div Figure 25. Vertical Scale = 400 mV/div SN65MLVD200A RECEIVER OUTPUT EYE PATTERN vs 100 Mbps, 215-1 PRBS, cL = 15 pF Horizontal Scale = 2 ns/div Figure 26.
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SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A www.ti.com SLLS573 – DECEMBER 2003 APPLICATION INFORMATION COMPARISON OF MLVD TO TIA/EIA-485 Receiver Input Threshold (Failsafe) The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65MLVD200ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65MLVD202ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65MLVD204ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65MLVD200ADR SOIC SN65MLVD202ADR SOIC D 8 2500 340.5 338.1 20.6 D 14 2500 333.2 345.9 28.6 SN65MLVD204ADR SOIC SN65MLVD205ADR SOIC D 8 2500 340.5 338.1 20.6 D 14 2500 333.2 345.9 28.
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