Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - transceivers LVDS, P2MP 1/1 SOIC 8

FEATURES APPLICATIONS

DESCRIPTION

LOGIC DIAGRAM (POSITIVE LOGIC)

SN65MLVD203, SN65MLVD207

SN65MLVD201, SN65MLVD206

SN65MLVD201 , SN65MLVD203

SN65MLVD206 , SN65MLVD207

SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007

www.ti.com

MULTIPOINT-LVDS LINE DRIVER AND RECEIVER

• Low-Power High-Speed Short-Reach

• Low-Voltage Differential 30- Ω to 55- Ω Line

Alternative to TIA/EIA-485

Drivers and Receivers for Signaling Rates

(1)

• Backplane or Cabled Multipoint Data and

Up to 200 Mbps

Clock Transmission

• Type-1 Receivers Incorporate 25 mV of

• Cellular Base Stations

Hysteresis

• Central-Office Switches

• Type-2 Receivers Provide an Offset (100 mV)

• Network Switches and Routers

Threshold to Detect Open-Circuit and Idle-Bus

Conditions

• Meets or Exceeds the M-LVDS Standard

TIA/EIA-899 for Multipoint Data Interchange

The SN65MLVD201, 203, 206, and 207 are

multipoint-low-voltage differential (M-LVDS) line

• Controlled Driver Output Voltage Transition

drivers and receivers, which are optimized to operate

Times for Improved Signal Quality

at signaling rates up to 200 Mbps. All parts comply

• -1 V to 3.4 V Common-Mode Voltage Range

with the multipoint low-voltage differential signaling

Allows Data Transfer With 2 V of Ground Noise

(M-LVDS) standard TIA/EIA-899. These circuits are

similar to their TIA/EIA-644 standard compliant LVDS

• Bus Pins High Impedance When Disabled or

counterparts, with added features to address

≤ 1.5 V

multipoint applications. The driver output has been

• 100-Mbps Devices Available (SN65MLVD200A,

designed to support multipoint buses presenting

202A, 204A, 205A)

loads as low as 30 Ω , and incorporates controlled

• M-LVDS Bus Power Up/Down Glitch Free

transition times to allow for stubs off of the backbone

transmission line.

The signaling rate of a line, is the number of voltage transitions

that are made per second expressed in the units bps (bits per

These devices have Type-1 and Type-2 receivers

second).

that detect the bus state with as little as 50 mV of

differential input voltage over a common-mode

voltage range of -1 V to 3.4 V. The Type-1 receivers

exhibit 25 mV of differential input voltage hysteresis

to prevent output oscillations with slowly changing

signals or loss of input. Type-2 receivers include an

offset threshold to provide a known output state

under open-circuit, idle-bus, and other faults

conditions. The devices are characterized for

operation from – 40 ° C to 85 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 2 4 6 ns tpHL Propagation delay time, high-to-low-level output 2 4 6 ns tr Output signal rise time 1 2.3 ns tf Output signal fall time 1 2.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION VCC IA or IY A/Y II D IB or IZ VAB or VYZ VA or VY B/Z VI VOS VB or VZ VA + VB 2 or VY + VZ 2 Figure 1. Driver Voltage and Current Definitions 3.32 kΩ A/Y VAB or VYZ D B/Z A. + _ 49.9 Ω -1 V ≤ Vtest ≤ 3.4 V 3.32 kΩ All resistors are 1% tolerance. Figure 2. Differential Output Voltage Test Circuit R1 24.9 Ω A/Y C1 1 pF D ≈ 1.3 V B/Z ≈ 0.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) A/Y D C1 1 pF C3 0.5 pF R1 Output 50 Ω B/Z C2 1 pF VCC VCC/2 Input 0V tpLH tpHL VSS 0.9VSS VP(H) Output 0V VP(L) 0.1V SS 0 V SS tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz, duty cycle = 50 5%. B.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) A/Y 0 V or VCC B/Z VA, VB, VY or VZ 1.62 kΩ , ±1% Figure 7.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 Table 1. Type-1 Receiver Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE VID VIC RECEIVER OUTPUT (1) VIA VIB 2.400 0.000 2.400 1.200 0.000 2.400 –2.400 1.200 L 3.800 3.750 0.050 3.775 H 3.750 3.800 –0.050 3.775 L –1.350 –1.400 0.050 –1.375 H –1.400 –1.350 –0.050 –1.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 1.2 V B RL 499 Ω R A Inputs CL RE VO + _ VTEST 15 pF VCC VTEST 1V A VCC RE VCC/2 0V tpZL Output tpLZ VCC VCC/2 VOL +0.5 V VOL R VTEST 0V 1.4 V A VCC RE VCC/2 0V tpZH tpHZ VO VOH VOH -0.5 V VCC/2 0V A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz, duty cycle = 50 5%. B.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 INPUTS VA -VB 0.2 V - Type 1 0.4 V - Type 2 CLOCK INPUT VA -VB 1/f0 VIC 1V Period Jitter IDEAL OUTPUT VOH VA VCC/2 PRBS INPUT VOL 1/f0 VB VOH ACTUAL OUTPUT VCC/2 Peak to Peak Jitter VOH VOL tc(n) tjit(per) = tc(n) -1/f0 OUTPUT V CC/2 VOL tjit(pp) A. All input pulses are supplied by an Agilent 8304A Stimulus System. B.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 20 20 16 ICC − Supply Current − mA ICC − Supply Current − mA VCC = 3.3 V TA = 25°C Driver 12 8 Receiver 4 16 Driver 12 Receiver 8 4 Receiver VID = 250 mV VIC = 1 V 0 10 50 30 90 70 VCC = 3.3 V TA = 25°C f = 100 MHz 0 110 −50 f − Frequency − MHz 70 Figure 14.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE 2 2 1.6 Driver Propagation Delay − ns Differential Output Voltage − V VCC = 3.3 V f = 1 MHz 1.2 0.8 0.4 1.8 tpLH 1.6 tpHL 1.4 1.2 VCC = 3.3 V TA = 25°C 0 0 1 −50 IO − Output Current − mA 10 50 −10 30 TA − Free-Air Temperature − °C Figure 17.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) ADDED DRIVER PEAK-TO-PEAK JITTER vs DATA RATE 60 VCC = 3.3 V TA = 25°C Input = PRBS 215−1 Added Driver Peak-To-Peak Jitter − ps Added Driver Peak-To-Peak Jitter − ps 60 ADDED DRIVER PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE 50 40 30 20 10 0 25 105 65 145 185 50 40 30 20 VCC = 3.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) SN65MLVD201 DRIVER OUTPUT EYE PATTERN 200 Mbps, 215–1 PRBS, RL = 50 Ω ADDED RECEIVER PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE Vertical Scale = 175 mV/div Added Receiver Peak-To-Peak Jitter − ps 400 320 240 160 80 0 −50 VCC = 3.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 APPLICATION INFORMATION Receiver Input Threshold (Failsafe) The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference.
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SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 LIVE INSERTION/GLITCH-FREE POWER UP/DOWN The SN65MLVD201/203/206/207 family of products offered by Texas Instruments provides a glitch-free powerup/down feature that prevents the M-LVDS outputs of the device from turning on during a powerup or powerdown event.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Jan-2008 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65MLVD201DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65MLVD203DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65MLVD206DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65MLVD201DR SOIC SN65MLVD203DR SOIC D 8 2500 340.5 338.1 20.6 D 14 2500 333.2 345.9 28.6 SN65MLVD206DR SOIC SN65MLVD207DR SOIC D 8 2500 340.5 338.1 20.6 D 14 2500 333.2 345.9 28.
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