Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 14

SN54ABT125, SN74ABT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Typical V

OLP

(Output Ground Bounce)

<1 V at V

= 5 V, T

= 25°C

D High-Drive Outputs (−32-mA I

, 64-mA I

)

D I

off

and Power-Up 3-State Support Hot

Insertion

D Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

SN54ABT125 ...J OR W PACKAGE

SN74ABT125 . . . D, DB, N, NS,

OR PW PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

3212019

910111213

3OE

2OE

1OE

4OE

GND

SN54ABT125 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SN74ABT125 . . . RGY PACKAGE

(TOP VIEW)

114

4OE

3OE

2OE

1OE

GND

description/ordering information

The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is

disabled when the associated output-enable (OE

) input is high.

These devices are fully specified for hot-insertion applications using I

off

and power-up 3-state. The I

off

circuitry

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74ABT125N SN74ABT125N

QFN − RGY Tape and reel SN74ABT125RGYR AB125

SOIC D

Tube SN74ABT125D

ABT125

−40°C to 85°C

SOIC − D

Tape and reel SN74ABT125DR

ABT125

40 C

85 C

SOP − NS Tape and reel SN74ABT125NSR ABT125

SSOP − DB Tape and reel SN74ABT125DBR AB125

TSSOP − PW Tape and reel SN74ABT125PWR AB125

CDIP − J Tube SNJ54ABT125J SNJ54ABT125J

−55°C to 125°C

CFP − W Tube SNJ54ABT125W SNJ54ABT125W

LCCC − FK Tube SNJ54ABT125FK SNJ54ABT125FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (25 pages)

PAGE 1
SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002 D Typical VOLP (Output Ground Bounce) D Latch-Up Performance Exceeds 500 mA Per <1 V at VCC = 5 V, TA = 25°C D D High-Drive Outputs (−32-mA IOH, 64-mA IOL) D Ioff and Power-Up 3-State Support Hot Insertion 12 4 11 5 10 6 9 7 8 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 3 12 4 11 10 5 9 6 7 8 SN54ABT125 . . .
PAGE 2
SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002 FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 4 5 3A 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . .
PAGE 3
SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002 recommended operating conditions (see Note 4) SN54ABT125 SN74ABT125 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage IOH High-level output current IOL Δt/Δv Δt/ΔVCC Power-up ramp rate 200 TA Operating free-air temperature −55 2 2 0.8 0 VCC V V 0.
PAGE 4
SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS TYP† SN54ABT125 MAX MIN SN74ABT125 MIN II = −18 mA VCC = 4.5 V, IOH = −3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = −3 mA 3 3 3 IOH = −24 mA 2 2 IOH = −32 mA 2* VCC = 4 4.5 5V −1.2 MAX VCC = 4.5 V, VCC = 4 4.
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SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER tPLH† tPHL † tPZH† tPZL† tPHZ tPLZ† † FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y VCC = 5 V, TA = 25°C SN54ABT125 SN74ABT125 MIN TYP MAX MIN MAX MIN MAX 1 3.2 4.6 1 6 1 4.9 1 2.5 4.6 1 6.2 1 4.9 1 3.
PAGE 6
SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ABT125DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74ABT125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ABT125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT125DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74ABT125DR SOIC D 14 2500 367.0 367.0 38.0 SN74ABT125DR SOIC D 14 2500 333.2 345.9 28.6 SN74ABT125NSR SO NS 14 2000 367.0 367.0 38.0 SN74ABT125PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74ABT125RGYR VQFN RGY 14 3000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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