Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 14

SN54ABT126, SN74ABT126

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCBS183H − FEBRUARY 1991 − REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Typical V

OLP

(Output Ground Bounce)

<1 V at V

= 5 V, T

= 25°C

D High-Impedance State During Power Up

and Power Down

D High-Drive Outputs (−32-mA I

, 64-mA I

)

D I

off

and Power-Up 3-State Support Hot

Insertion

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

SN54ABT126 ...J PACKAGE

SN74ABT126 . . . D, DB, N, NS,

OR PW PACKAGE

(TOP VIEW)

SN54ABT126 . . . FK PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

3212019

910111213

3OE

2OE

1OE

4OE

GND

NC − No internal connection

SN74ABT126 . . . RGY PACKAGE

(TOP VIEW)

114

4OE

3OE

2OE

1OE

GND

description/ordering information

The ’ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled

when the associated output-enable (OE) input is low.

When V

is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown

resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74ABT126RGYR AB126

PDIP − N Tube SN74ABT126N SN74ABT126N

SOIC D

Tube SN74ABT126D

ABT126

40°Cto85°C

SOIC − D

Tape and reel SN74ABT126DR

ABT126

−40°C to 85°C

SOP − NS Tape and reel SN74ABT126NSR ABT126

SSOP − DB Tape and reel SN74ABT126DBR AB126

TSSOP PW

Tube SN74ABT126PW

AB126

TSSOP − PW

Tape and reel SN74ABT126PWR

AB126

55°C to 125°C

CDIP − J Tube SNJ54ABT126J SNJ54ABT126J

−55°C to 125°C

LCCC − FK Tube SNJ54ABT126FK SNJ54ABT126FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (20 pages)

PAGE 1
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 D Typical VOLP (Output Ground Bounce) D Ioff and Power-Up 3-State Support Hot <1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down D D High-Drive Outputs (−32-mA IOH, 64-mA IOL) D SN54ABT126 . . . J PACKAGE SN74ABT126 . . .
PAGE 2
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y H H H H L L L X Z logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 3A 4 5 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, and RGY packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . .
PAGE 3
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 recommended operating conditions (see Note 4) SN54ABT126 SN74ABT126 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage IOH High-level output current IOL Δt/Δv Δt/ΔVCC Power-up ramp rate 200 TA Operating free-air temperature −55 2 2 0.8 0 0 V V 0.
PAGE 4
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 5 and Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y VCC = 5 V, TA = 25°C TYP MAX MIN MAX MIN MAX 1 2.9 4.9 1 7.3 1 6.3 1 2.5 5.1 1 5.9 1 5.7 1 4.4 5.8 1 5.3 1 6.5 1 4.4 5.
PAGE 5
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V Data Input 0V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V Input Output Control 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74ABT126DBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DB 14 2000 330.0 16.4 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74ABT126DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ABT126NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT126DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74ABT126DR SOIC D 14 2500 367.0 367.0 38.0 SN74ABT126NSR SO NS 14 2000 367.0 367.0 38.0 SN74ABT126PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74ABT126RGYR VQFN RGY 14 3000 367.0 367.0 35.
PAGE 10
PAGE 11
PAGE 12
PAGE 13
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 19
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.