Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74ABT SSOP 56

SN54ABT162500, SN74ABT162500

18-BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

Widebus

 Family

B-Port Outputs Have Equivalent 25-Ω

Series Resistors, So No External Resistors

Are Required

State-of-the-Art

EPIC-

ΙΙ

 BiCMOS Design

Significantly Reduces Power Dissipation

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Typical V

OLP

(Output Ground Bounce)

< 0.8 V at V

= 5 V, T

= 25°C

High-Impedance State During Power Up

and Power Down

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 500 mA

Per JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic Shrink

Small-Outline (DL) Package and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

These 18-bit universal bus transceivers combine

D-type latches and D-type flip-flops to allow data

flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA

), latch-enable

(LEAB and LEBA), and clock (CLKAB

and

CLKBA

) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the

A data is latched if CLKAB

is held at a high or low logic level. If LEAB is low, the A data is stored in the

latch/flip-flop on the high-to-low transition of CLKAB

. Output-enable OEAB is active high. When OEAB is high,

the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA

, LEBA, and CLKBA. The output enables are

complementary (OEAB is active high and OEBA

is active low).

The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors

to reduce overshoot and undershoot.

SN54ABT162500 ...WD PACKAGE

SN74ABT162500 . . . DL PACKAGE

(TOP VIEW)

OEAB

LEAB

GND

A10

A11

A12

GND

A13

A14

A15

A16

A17

GND

A18

OEBA

LEBA

GND

CLKAB

GND

B10

B11

B12

GND

B13

B14

B15

B16

B17

GND

B18

CLKBA

GND

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (12 pages)

PAGE 1
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 D D D D D D D D D D SN54ABT162500 . . . WD PACKAGE SN74ABT162500 . . .
PAGE 2
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 description (continued) When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.
PAGE 3
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 logic symbol† OEAB CLKAB LEAB 1 55 2 27 OEBA CLKBA LEBA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 30 28 3 EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 1 1 4 1 6D 54 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18
PAGE 4
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 logic diagram (positive logic) OEAB CLKAB LEAB LEBA CLKBA OEBA A1 1 55 2 28 30 27 3 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 3) SN54ABT162500 VCC VIH Supply voltage VIL VI Low-level input voltage High-level input voltage SN74ABT162500 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage 0 0.
PAGE 6
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A port TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOH B port VCC = 4.5 V, VCC = 5 V, 5V VCC = 4 4.5 VOL A port VCC = 4 4.5 5V B port VCC = 4.5 V, MIN –1.2 SN74ABT162500 MIN –1.2 2.5 2.
PAGE 7
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT162500 MIN fclock tw tsu Clock frequency SN74ABT162500 MIN 150 LEAB or LEBA high Pulse duration 2.5 3 3 A before CLKAB↓ 3.3 3.3 B before CLKBA↓ 3.3 3.
PAGE 8
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input 3V 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 1.5 V 0V tPLH 1.5 V VOL tPLZ 3.5 V 1.5 V tPZH VOH 1.5 V 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT162500DLR Package Package Pins Type Drawing SSOP DL 56 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 11.35 18.67 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT162500DLR SSOP DL 56 1000 346.0 346.0 49.
PAGE 12
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