Datasheet

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SN54ABT16543, SN74ABT16543

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

Widebus

 Family

State-of-the-Art

EPIC-

ΙΙ

 BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical V

OLP

(Output Ground Bounce) < 1 V

at V

= 5 V, T

= 25°C

Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA I

, 64-mA I

)

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’ABT16543 16-bit registered transceivers

contain two sets of D-type latches for temporary

storage of data flowing in either direction. The

’ABT16543 can be used as two 8-bit transceivers

or one 16-bit transceiver. Separate latch-enable

(LEAB

or LEBA) and output-enable (OEAB or

OEBA

) inputs are provided for each register to

permit independent control in either direction of

data flow.

The A-to-B enable (CEAB) input must be low to

enter data from A or to output data from B. If CEAB

is low and LEAB is low, the A-to-B latches are

transparent; a subsequent low-to-high transition

of LEAB puts the A latches in the storage mode.

With CEAB

and OEAB both low, the 3-state

B outputs are active and reflect the data present

at the output of the A latches. Data flow from B to

A is similar but requires using the CEBA, LEBA,

and OEBA inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16543 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT16543 is characterized for operation from –40°C to 85°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

SN54ABT16543 . . . WD PACKAGE

SN74ABT16543 . . . DGG OR DL PACKAGE

(TOP VIEW)

1OEAB

1LEAB

1CEAB

GND

1A1

1A2

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2CEAB

2LEAB

2OEAB

1OEBA

1LEBA

1CEBA

GND

1B1

1B2

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

2B7

2B8

GND

2CEBA

2LEBA

2OEBA

Summary of content (16 pages)

PAGE 1
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 D D D D D D D D SN54ABT16543 . . . WD PACKAGE SN74ABT16543 . . .
PAGE 2
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 FUNCTION TABLE† (each 8-bit section) INPUTS CEAB LEAB OEAB A OUTPUT B H X X X Z X X H X Z L H L X L L L L B0‡ L L L L H H † A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA.
PAGE 3
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 logic symbol† 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 56 54 55 1 3 2 29 31 30 28 26 27 2LEAB 1A1 1EN3 G1 1C5 2EN4 G2 2C6 7EN9 G7 7C11 8EN10 G8 8C12 5 3 6D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 2A3 2A4 2A5 2A6 2A7 2A8 4 52 51 8 49 9 48 10 47 12 45 13 44 14 43 15 9 12D 2A2 5D 16 11D 10 42 41 17 40 19 38 20 37 21 36 23 34 2
PAGE 4
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 logic diagram (positive logic) 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 56 54 55 1 3 2 C1 5 1D 52 1B1 C1 1D To Seven Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1 29 31 30 28 26 27 C1 15 1D C1 1D To Seven Other Channels 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 42 2B1
PAGE 5
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 6
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN TA = 25°C TYP† MAX SN54ABT16543 MIN –1.2 MAX SN74ABT16543 MIN –1.2 –1.2 2.5 2.5 2.
PAGE 7
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT16543 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LE A or B tPZH tPZL OE A or B tPHZ tPLZ OE A or B tPZH tPZL CE A or B tPHZ tPLZ CE A or B VCC = 5 V, TA = 25°C MIN MAX MIN
PAGE 8
SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ABT16543DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74ABT16543DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT16543DGGR TSSOP DGG 56 2000 367.0 367.0 45.0 SN74ABT16543DLR SSOP DL 56 1000 367.0 367.0 55.
PAGE 13
MECHANICAL DATA MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91) 0.009 (0,23) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 0.390 (9,91) 0.370 (9,40) 0.370 (9,40) 0.250 (6,35) 48 1 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 25 24 NO. OF LEADS** 48 56 A MAX 0.640 (16,26) 0.740 (18,80) A MIN 0.610 (15,49) 0.710 (18,03) 4040176 / D 10/97 NOTES: A. B. C. D. E.
PAGE 14
PAGE 15
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.