SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 D D D D D Member of the Texas Instruments Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Compatible With IEEE Std 1149.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 description The SN74ABT18502 scan test device with an 18-bit universal bus transceiver is a member of the Texas Instruments SCOPE testability IC family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port (TAP) interface.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 functional block diagram Boundary-Scan Register (BSR) 1LEAB 1CLKAB 60 59 1OEAB 62 1LEBA 54 1CLKBA 1OEBA 55 53 One of Nine Channels 1A1 C1 C1 1D 1D 51 63 C1 1D 1B1 C1 1D 2LEAB 22 2CLKAB 2OEAB 2LEBA 2CLKBA 23 21 28 27 2OEBA 30 One of Nine Channels 2A1 C1 C1 1D 1D 40 10 C1 1D 2B1 C1 1D Bypass Register Boundary-Control Register (BCR) Identification Register (IDR) TDI TMS TCK VCC 24 VCC 5
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 Terminal Functions PIN NAME DESCRIPTION GND Ground TCK Test clock. One of four pins required by IEEE Std 1149.1-1990. Test operations of the device are synchronous to the test clock. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. TDI Test data input. One of four pins required by IEEE Std 1149.1-1990.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 test architecture Serial test information is conveyed by means of a four-wire test bus or TAP that conforms to IEEE Std 1149.1-1990. Test instructions, test data, and test control signals are all passed along this serial test bus. The TAP controller monitors two signals from the test bus, namely TCK and TMS.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 state diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram is shown in Figure 1 and is in accordance with IEEE Std 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As illustrated, the TAP controller consists of sixteen states.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states used to end a DR scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the DR. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 register overview With the exception of the bypass register and device IDR, any test register can be thought of as a serial shift register with a shadow latch on each bit. The bypass register and device IDR differ in that they contain only a shift register.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 data register (DR) boundary-scan register (BSR) The BSR is 84 bits long. It contains one BSC for each normal-function input pin and two BSCs for each normal-function I/O pin (one for input data and one for output data).
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 boundary-control register (BCR) The BCR is 21 bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA with input masking, and binary count up (COUNT). Table 5 shows the test operations that are decoded by the BCR. During Capture-DR, the contents of the BCR are not changed.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 Table 3.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 boundary scan This instruction conforms to the IEEE Std 1149.1-1990 EXTEST and INTEST instructions. The BSR is selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 BCR scan The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed. BCR opcodes The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 5. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 pseudorandom pattern generation (PRPG) A pseudorandom pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 2B9-I 2B8-I 2B7-I 2B6-I 2B5-I 2B4-I 2B3-I 2B2-I 2B1-I 1B9-I 1B8-I 1B7-I 1B6-I 1B5-I 1B4-I 1B3-I 1B2-I 1B1-I 2A9-O 2A8-O 2A7-O 2A6-O 2A5-O 2A4-O 2A3-O 2A2-O 2A1-O 1A9-O 1A8-O 1A7-O 1A6-O 1A5-O 1A4-O 1A3-O 1A2-O 1A1-O = Figure 5.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 parallel signature analysis (PSA) Data appearing at the selected device input pins is compressed into a 36-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 2B8-I 2B7-I 2B6-I 2B5-I 2B4-I 2B3-I 2B2-I 2B1-I 1B9-I 1B8-I 1B7-I 1B6-I 1B5-I 1B4-I 1B3-I 1B2-I 1B1-I 2A9-O 2A8-O 2A7-O 2A6-O 2A5-O 2A4-O 2A3-O 2A2-O 2A1-O 1A9-O 1A8-O 1A7-O 1A6-O 1A5-O 1A4-O 1A3-O 1A2-O 1A1-O MASKX.X 2B9-I = = Figure 7.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 2B8-I 2B7-I 2B6-I 2B5-I 2B4-I 2B3-I 2B2-I 2B1-I 1B9-I 1B8-I 1B7-I 1B6-I 1B5-I 1B4-I 1B3-I 1B2-I 1B1-I 2A9-O 2A8-O 2A7-O 2A6-O 2A5-O 2A4-O 2A3-O 2A2-O 2A1-O 1A9-O 1A8-O 1A7-O 1A6-O 1A5-O 1A4-O 1A3-O 1A2-O 1A1-O MASKX.X 2B9-I = = Figure 9.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 simultaneous PSA and COUNT (PSA/COUNT) MASKX.X Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER MASKX.X SCBS753 – FEBRUARY 2002 2B9-I 2B8-I 2B7-I 2B6-I 2B5-I 2B4-I 2B3-I 2B2-I 2B1-I 1B9-I 1B8-I 1B7-I 1B6-I 1B5-I 1B4-I 1B3-I 1B2-I 1B1-I 2A8-O 2A7-O 2A6-O 2A5-O 2A4-O 2A3-O 2A2-O 2A1-O MSB 2A9-O = LSB = 1A9-O 1A8-O 1A7-O 1A6-O 1A5-O 1A4-O 1A3-O 1A2-O 1A1-O Figure 11.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 timing description All test operations of the SN74ABT18502 are synchronous to the TCK signal. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Update-DR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Exit1-DR Capture-DR Update-IR Select-DR-Scan ÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Exit1-IR Shift-IR Capture-IR Select-IR-Scan TAP Controller State Select-DR-Scan TDO ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Run-Test/Idle TDI Test-Logic
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 recommended operating conditions (see Note 3) MIN MAX 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC – 32 mA Low-level output current 64 mA ∆t /∆v Input transition rise or fall rate 10 ns / V High-level input voltage 2 V 0.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 13) fclock Clock frequency tw Pulse duration CLKAB or CLKBA MHz 3.5 3.
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 13)1234 PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ 26 FROM (INPUT) TO (OUTPUT) TCK TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 5 V, TA = 25°C MIN
SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 3V 1.5 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 0V tPHL 1.5 V 1.5 V tPLH VOH Output 1.5 V 1.5 V 0V 1.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT18502PMR Package Package Pins Type Drawing LQFP PM 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.1 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT18502PMR LQFP PM 64 1000 367.0 367.0 45.
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
