Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Custom logic Scan test device with bis transceiver SOIC 24

SN54ABT8245, SN74ABT8245

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

SCOPE

 Family of Testability Products

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port

and Boundary-Scan Architecture

Functionally Equivalent to ’F245 and

’ABT245 in the Normal-Function Mode

SCOPE

 Instruction Set:

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,

and HIGHZ

– Parallel-Signature Analysis at Inputs

With Masking Option

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Even-Parity Opcodes

Two Boundary-Scan Cells per I/O for

Greater Flexibility

State-of-the-Art

EPIC-

ΙΙ

 BiCMOS Design

Significantly Reduces Power Dissipation

Package Options Include Plastic

Small-Outline Packages (DW), Ceramic

Chip Carriers(FK), and Standard Ceramic

DIPs (JT)

description

The ’ABT8245 scan test devices with octal bus

transceivers are members of the Texas Instru-

ments SCOPE testability integrated-circuit

family. This family of devices supports IEEE

Standard 1149.1-1990 boundary scan to facilitate

testing of complex circuit-board assemblies. Scan

access to the test circuitry is accomplished via the

4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the ’F245 and ’ABT245 octal bus transceivers.

The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins

or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the

functional operation of the SCOPE octal bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE

) inputs. Data transmission is

allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. The

output-enable (OE

) input can be used to disable the device so that the buses are effectively isolated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

321

13 14

TDI

TCK

TMS

TDO

DIR

15 16 17 18

GND

28 27 26

SN54ABT8245 . . . JT PACKAGE

SN74ABT8245 . . . DW PACKAGE

(TOP VIEW)

SN54ABT8245 . . . FK PACKAGE

(TOP VIEW)

DIR

GND

TDO

TMS

TDI

TCK

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 D D D D D D SN54ABT8245 . . . JT PACKAGE SN74ABT8245 . . . DW PACKAGE (TOP VIEW) Members of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Functionally Equivalent to ’F245 and ’ABT245 in the Normal-Function Mode SCOPE  Instruction Set: – IEEE Standard 1149.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 description (continued) In the test mode, the normal operation of the SCOPE  bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 functional block diagram Boundary-Scan Register OE DIR A1 24 1 2 23 B1 One of Eight Channels Bypass Register Boundary-Control Register VCC TDI 11 14 TDO Instruction Register VCC TMS TCK 12 13 TAP Controller Pin numbers shown are for the DW and JT packages.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 Terminal Functions TERMINAL NAME 4 DESCRIPTION A1 – A8 Normal-function A-bus I/O ports. See function table for normal-mode logic. B1 – B8 Normal-function B-bus I/O ports. See function table for normal-mode logic. DIR Normal-function direction-control input. See function table for normal-mode logic. GND Ground OE Normal-function output-enable input.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 state diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As illustrated, the TAP controller consists of 16 states.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 register overview With the exception of the bypass register, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 data register description boundary-scan register The boundary-scan register (BSR) is 36 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin, two BSCs for each normal-function I/O pin (one for input data and one for output data), and one BSC for each of the internally decoded output-enable signals (OEA and OEB).
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 boundary-control register The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations decoded by the BCR.
PAGE 11
SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 control boundary to high impedance This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2 – 0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 4.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 parallel-signature analysis (PSA) MASKX Data appearing at the selected device input pins is compressed into a 16-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
PAGE 16
SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
PAGE 18
SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 timing description All test operations of the ’ABT8245 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK.
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Update-DR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Exit1-DR Capture-DR Update-IR Select-DR-Scan ÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Exit1-IR Shift-IR Capture-IR Select-IR-Scan TAP Controller State Select-DR-Scan TDO ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Run-T
PAGE 20
SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 recommended operating conditions (see Note 3) SN54ABT8245 SN74ABT8245 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC – 24 Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate 10 10 ns / V 85 °C High-level input voltage 2 2 0.
PAGE 21
SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 13) SN54ABT8245 fclock tw tsu th td tr SN74ABT8245 MIN MAX MIN MAX 50 0 50 Clock frequency TCK 0 Pulse duration TCK high or low 5 5 A or B or DIR or OE before TCK↑ 7 5 Setup time Hold time Delay time UNIT MHz ns ns TDI befor
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 13) SN54ABT8245 PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TCK TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO VCC = 5 V, TA = 25°C MIN TYP 50 90 MIN
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SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 3V 1.5 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 0V tPHL 1.5 V 1.5 V VOL VOH Output 1.5 V 1.5 V 0V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT8245DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT8245DWR SOIC DW 24 2000 367.0 367.0 45.
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MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.
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