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SN54ABT833, SN74ABT833

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

State-of-the-Art

EPIC-

ΙΙ

 BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical V

OLP

(Output Ground Bounce) < 1 V

at V

= 5 V, T

= 25°C

High-Drive Outputs (–32-mA I

64-mA I

)

Parity Error Flag With Parity

Generator/Checker

Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Plastic (NT) and

Ceramic (JT) DIPs

description

The ’ABT833 8-bit to 9-bit parity transceivers are

designed for communication between data buses.

When data is transmitted from the A bus to the

B bus, a parity bit is generated. When data is

transmitted from the B bus to the A bus with its

corresponding parity bit, the open-collector

parity-error (ERR

) output indicates whether or not

an error in the B data has occurred. The

output-enable (OEA

and OEB) inputs can be used

to disable the device so that the buses are

effectively isolated. The ’ABT833 provide true

data at their outputs.

A 9-bit parity generator/checker generates a

parity-odd (PARITY) output and monitors the

parity of the I/O ports with the ERR flag. ERR is

clocked into the register on the rising edge of the

clock (CLK) input. The error flag register is cleared

with a low pulse on the clear (CLR

) input. When

both OEA and OEB are low, data is transferred

from the A bus to the B bus and inverted parity is

generated. Inverted parity is a forced error

condition that gives the designer more system

diagnostic capability.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

OEA

ERR

CLR

GND

PARITY

OEB

CLK

SN54ABT833 . . . JT PACKAGE

SN74ABT833 ... DW OR NT PACKAGE

(TOP VIEW)

3212827

12 13

426

14 15 16 17 18

ERR

CLR

GND

CLK

OEB

PARITY

OEA

SN54ABT833 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Summary of content (14 pages)

PAGE 1
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 D D D D D D SN54ABT833 . . . JT PACKAGE SN74ABT833 . . . DW OR NT PACKAGE (TOP VIEW) OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. ERR is clocked into the register on the rising edge of the clock (CLK) input.
PAGE 2
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 description (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT833 is characterized for operation over the full military temperature range of –55°C to 125°C.
PAGE 3
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 logic diagram (positive logic) A1–A8 2–9 8x 8 16–23 8 B1–B8 EN 8x 8 EN OEB 14 15 OEA 1 8 PARITY 8 1 MUX 1 2k 9 1 P 1 G1 1D CLK CLR 13 10 ERR C1 11 R Pin numbers shown are for the DW, JT, and NT packages.
PAGE 4
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 error-flag waveforms H OEB L H OEA L Even Bi + PARITY Odd tsu th H CLK L tw tsu tw H CLR L tPHL tPLH H ERR L absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 5
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 recommended operating conditions (see Note 3) SN54ABT833 VCC VIH Supply voltage VIL VI Low-level input voltage VOH IOH High-level output voltage ERR High-level output current Except ERR IOL ∆t/∆v Low-level output current High-level input voltage SN74ABT833 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.
PAGE 6
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH All outputs except ERR TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL Vhys IOH VCC = 4 4.5 5V MIN TA = 25°C TYP† MAX SN54ABT833 MIN –1.2 MAX SN74ABT833 MIN –1.2 –1.2 2.5 2.5 2.
PAGE 7
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN tw Pulse duration tsu Setup time before CLK↑ th Hold time after CLK↑ MAX SN54ABT833 MIN MAX SN74ABT833 MIN CLK high or low 3 3 3 CLR low 3 3 3 B or PARITY high 9.8 9.8 9.8 B or PARITY low 8.1 8.1 8.
PAGE 8
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 500 Ω ERR S1 tPHL tPLH 7V 7V LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V 1.5 V th 3V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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