Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Custom logic Scan test device with bus tranceiver and registers SOIC 28

 

   

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SCBS123F − AUGUST 1992 − REVISED APRIL 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Members of the Texas Instruments

SCOPE  Family of Testability Products

D Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

D Functionally Equivalent to ’F646 and

’ABT646 in the Normal-Function Mode

D SCOPE  Instruction Set

− IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,

and HIGHZ

− Parallel-Signature Analysis at Inputs

With Masking Option

− Pseudorandom Pattern Generation From

Outputs

− Sample Inputs/Toggle Outputs

− Binary Count From Outputs

− Even-Parity Opcodes

D Two Boundary-Scan Cells Per I/O for

Greater Flexibility

D State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

D Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DL) Packages, Ceramic Chip

Carriers (FK), and Standard Ceramic DIPs

(JT)

description

The ’ABT8646 and scan-test devices with octal

bus transceivers and registers are members of the

Texas Instruments SCOPE testability

integrated-circuit family. This family of devices

supports IEEE Standard 1149.1-1990 boundary

scan to facilitate testing of complex circuit-board

assemblies. Scan access to the test circuitry is

accomplished via the 4-wire test access port

(TAP) interface.

In the normal mode, these devices are functionally equivalent to the ’F646 and ’ABT646 octal bus transceivers

and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing

at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does

not affect the functional operation of the SCOPE octal bus transceivers and registers.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments.

CLKAB

SAB

DIR

GND

TDO

TMS

CLKBA

SBA

TDI

TCK

321

13 14

TDI

TCK

TMS

TDO

SBA

CLKBA

CLKAB

SAB

DIR

15 16 17 18

28 27 26

SN54ABT8646 . . . JT PACKAGE

SN74ABT8646 . . . DL OR DW PACKAGE

(TOP VIEW)

SN54ABT8646 . . . FK PACKAGE

(TOP VIEW)

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Summary of content (34 pages)

PAGE 1
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 D Members of the Texas Instruments SCOPE  Family of Testability Products D Compatible With the IEEE Standard SN54ABT8646 . . . JT PACKAGE SN74ABT8646 . . . DL OR DW PACKAGE (TOP VIEW) 1149.
PAGE 2
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 description (continued) Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses.
PAGE 3
26 OE L 3 DIR L 27 SBA L 2 SAB X 28 1 CLKAB CLKBA X X BUS B BUS A BUS A BUS B SCBS123F − AUGUST 1992 − REVISED APRIL 2004 26 OE L 3 DIR H 1 28 CLKAB CLKBA X ↑ X ↑ ↑ ↑ 2 SAB L 2 SAB X X X 27 SBA X BUS B BUS A BUS B BUS A 3 DIR X X X 28 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B REAL-TIME TRANSFER BUS B TO BUS A 26 OE X X H 1 CLKAB X 27 SBA X X X STORAGE FROM A, B, OR A AND B 26 OE L L 3 DIR L H 1 CLKA
PAGE 4
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 functional block diagram Boundary-Scan Register OE DIR CLKBA SBA CLKAB SAB 26 3 28 27 1 2 C1 1D A1 4 25 C1 1D One of Eight Channels Bypass Register Boundary-Control Register VCC TDI 13 16 Instruction Register VCC TMS TCK 14 15 TAP Controller Pin numbers shown for the DL, DW, and JT packages.
PAGE 5
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 Terminal Functions TERMINAL NAME DESCRIPTION A1−A8 Normal-function A-bus I/O ports. See function table for normal-mode logic. B1−B8 Normal-function B-bus I/O ports. See function table for normal-mode logic. CLKAB, CLKBA Normal-function clock inputs. See function table for normal-mode logic. DIR Normal-function direction-control input. See function table for normal-mode logic.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 state diagram description The TAP controller is a synchronous finite-state machine that provides test control signals throughout the device. The state diagram shown in Figure 2 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states, based on the level of TMS at the rising edge of TCK. As shown, the TAP controller consists of 16 states.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 register overview With the exception of the bypass register, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 data register description boundary-scan register The boundary-scan register (BSR) is 40 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin, two BSCs for each normal-function I/O pin (one for input data and one for output data), and one BSC for each of the internally decoded output-enable signals (OEA and OEB).
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 boundary-control register The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 control boundary to high impedance This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR.
PAGE 14
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2−0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 4.
PAGE 15
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 pseudorandom pattern generation (PRPG) A pseudorandom pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK.
PAGE 16
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 parallel-signature analysis (PSA) MASKX Data appearing at the selected device input pins is compressed into a 16-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
PAGE 17
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
PAGE 18
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
PAGE 19
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 timing description All test operations of the ’ABT8646 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK.
PAGE 20
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Test-Logic-Reset Select-IR-Scan Update-DR Exit1-DR Capture-DR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Select-DR-Scan ÎÎ ÎÎ Select-DR-Scan Shift-IR Capture-IR Select-IR-Scan Select-DR-Scan Run-Test/Idle TAP Controller State Test-Logic-Reset TDO ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Update-IR ÎÎÎÎÎÎÎÎ
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 recommended operating conditions (see Note 3) SN54ABT8646 SN74ABT8646 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC −24 Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 10 10 ns/V 85 °C High-level input voltage 2 2 0.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = −18 mA IOH = −3 mA VCC = 5 V, VCC = 4.5 V VOL II VCC = 4.5 V CLK, DIR, OE, S, TCK MIN TA = 25°C TYP† MAX −1.2 3 2 2 IOH = −32 mA IOL = 48 mA 2* IOL = 64 mA ±1 ±100 ±100 ±100 VI or VO ≤ 4.
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SCBS123F − AUGUST 1992 − REVISED APRIL 2004 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14) SN54ABT8646 SN74ABT8646 MIN MAX MIN MAX 100 0 100 UNIT fclock tw Clock frequency CLKAB or CLKBA 0 Pulse duration CLKAB or CLKBA high or low 3 3 MHz ns tsu th Setup time A before CLKAB↑ or B before CLKBA↑ 4.7 4.
PAGE 24
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14) SN54ABT8646 PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLKAB or CLKBA A or B B or A CLKAB or CLKBA B or A SAB or SBA B or A DIR B or A OE B or A DI
PAGE 25
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 14) SN54ABT8646 PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TCK TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO VCC = 5 V, TA = 25°C MIN TYP MIN
PAGE 26
SCBS123F − AUGUST 1992 − REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.
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