Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74ABTH LQFP 64

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A

SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

SCOPE

 Family of Testability Products

Members of the Texas Instruments

Widebus

 Family

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port

and Boundary-Scan Architecture

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Bus Hold on Data Inputs Eliminates the

Need for External Pullup Resistors

B-Port Outputs of ’ABTH182502A Devices

Have Equivalent 25-Ω Series Resistors, So

No External Resistors Are Required

State-of-the-Art

EPIC-

ΙΙ

 BiCMOS Design

One Boundary-Scan Cell Per I/O

Architecture Improves Scan Efficiency

SCOPE

Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Packaged in 64-Pin Plastic Thin Quad Flat

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

TMS

1CLKBA

1A2

1A1

1OEAB

GND

1LEAB

1CLKAB

TDO

1LEBA

1OEBA

GND

1B1

1B2

1B3

1B4

1B5

1B6

GND

1B7

1B8

1B9

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

2A1

2A2

2A3

GND

2A4

2A5

2A6

TCK

2CLKBA

2LEBA

2A9

GND

2OEAB

2LEAB

2CLKAB

TDI

2A7

2A8

GND

2OEBA

2B9

2B8

SN54ABTH18502A, SN54ABTH182502A . . . HV PACKAGE

(TOP VIEW)

NC – No internal connection

28 29 30 31 32 33 34

87 65493168672

35 36 37 38 39

66 65

64 63 62 61

40 41 42 43

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

Summary of content (43 pages)

PAGE 1
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 D D D D D D D D Members of the Texas Instruments SCOPE  Family of Testability Products Members of the Texas Instruments Widebus  Family Compatible With the IEEE Standard 1149.
PAGE 2
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 1A2 1A1 1OEAB GND 1LEAB 1CLKAB TDO V CC TMS 1CLKBA 1LEBA 1OEBA GND 1B1 1B2 1B3 SN74ABTH18502A, SN74ABTH182502A . . .
PAGE 3
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 description (continued) Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK).
PAGE 4
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 functional block diagram Boundary-Scan Register 1LEAB 1CLKAB 1OEAB 1LEBA 1CLKBA 1OEBA 1A1 60 59 VCC 62 54 55 VCC 53 C1 C1 1D 1D 63 51 C1 1D 1B1 C1 1D One of Nine Channels 2LEAB 2CLKAB 2OEAB 2LEBA 22 23 VCC 21 28 2CLKBA 27 VCC 30 2OEBA 2A1 C1 C1 1D 1D 10 40 C1 1D 2B1 C1 1D One of Nine Channels Bypass Register Boundar
PAGE 5
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 Terminal Functions TERMINAL NAME DESCRIPTION 1A1–1A9, 2A1–2A9 Normal-function A-bus I/O ports. See function table for normal-mode logic. 1B1–1B9, 2B1–2B9 Normal-function B-bus I/O ports. See function table for normal-mode logic. 1CLKAB, 1CLKBA, 2CLKAB, 2CLKBA GND Normal-function clock inputs. See function table for normal-mode logic.
PAGE 6
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS.
PAGE 7
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 state diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.
PAGE 8
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 Shift-DR (continued) While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e.
PAGE 9
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 register overview With the exception of the bypass and device-identification registers, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that they contain only a shift register.
PAGE 10
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 data register description boundary-scan register The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and output data).
PAGE 11
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 boundary-control register The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test (RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA, and binary count up (COUNT).
PAGE 12
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 device-identification register The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer, part number, and version of this device.
PAGE 13
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3.
PAGE 14
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 bypass scan This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. control boundary to high impedance This instruction conforms to the IEEE Standard 1149.
PAGE 15
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state.
PAGE 16
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each falling edge of TCK.
PAGE 17
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 pseudo-random pattern generation (PRPG) (continued) 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A
PAGE 18
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 parallel-signature analysis (PSA) Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK.
PAGE 19
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 parallel-signature analysis (PSA) (continued) 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O
PAGE 20
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK.
PAGE 21
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 simultaneous PSA and PRPG (PSA/PRPG) (continued) 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I
PAGE 22
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK.
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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 simultaneous PSA and binary count up (PSA/COUNT) (continued) 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O MSB 2A9-I/O LSB = = 1A9-I/O 1A8-I/O 1A7-I
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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 timing description All test operations of the ’ABTH18502A and ’ABTH182502A are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK.
PAGE 25
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 timing description (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Select-IR-Scan Select-DR-Scan Update-DR Exit1-DR Capture-DR Select-DR-Scan Update-IR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Test-Logic-Reset ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Exit1-IR Shift-IR Capture-IR Select-IR-Scan TAP C
PAGE 26
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 recommended operating conditions SN54ABTH18502A SN74ABTH18502A MIN MAX MIN MAX 4.5 5.5 4.5 5.
PAGE 27
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ABTH18502A PARAMETER VIK VOH VOL II IIH IIL TEST CONDITIONS TA = 25°C TA = –55°C to 125°C † MIN MAX MIN MAX TYP VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4.5 V, IOH = –3 mA IOH = –24 mA VCC = 4.
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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74ABTH18502A PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL II IIH IIL VCC = 4 4.
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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14)1 SN54ABTH18502A fclock Clock frequency tw Pulse duration tsu Setup time MIN MAX 0 100 CLKAB or CLKBA MAX 0 100 3.8 3.5 LEAB or LEBA high 3.5 3.5 3.5 3.5 4.0 3.
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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14)1 SN54ABTH18502A PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLKAB or CLKBA A or B B or A CLKAB or CLKBA B or A LEAB or LEBA B or
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SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 14) PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TCK TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO VCC
PAGE 32
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 recommended operating conditions SN54ABTH182502A VCC VIH Supply voltage VIL VI Low-level input voltage MAX MIN MAX 4.5 5.5 4.5 5.
PAGE 33
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK port TDO A port, TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOH B port VCC = 4.5 V, VCC = 5 V, 5V VCC = 4 4.5 A port, port TDO VCC = 4 4.5 5V B port VCC = 4 4.
PAGE 34
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER Ci Control inputs TEST CONDITIONS MIN TA = 25°C TYP† MAX VI = 2.5 V or 0.5 V Cio A or B ports VO = 2.5 V or 0.5 V Co TDO VO = 2.5 V or 0.5 V † All typical values are at VCC = 5 V.
PAGE 35
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14)12 PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLKAB or CLKBA tPLH tPHL A B tPLH tPHL B A tPLH tPHL CLKAB B tPLH tPHL CLKBA A tPLH tPHL LEAB B tPLH tPHL LEBA A tPZH t
PAGE 36
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 1.5 V 3V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 1.5 V 0V 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABTH18502APMR Package Package Pins Type Drawing LQFP PM 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.1 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABTH18502APMR LQFP PM 64 1000 367.0 367.0 45.
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MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.