Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74AC SOIC 14

 

   

SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 6.5 ns at 5 V

SN54AC10 ... J OR W PACKAGE

SN74AC10 ... D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

GND

3212019

910111213

SN54AC10 . . . FK PACKAGE

(TOP VIEW)

GND

NC − No internal connection

description/ordering information

The ’AC10 devices contain three independent 3-input NAND gates. The devices perform the Boolean function

Y = A

• B • C or Y = A + B + C in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC10N SN74AC10N

SOIC − D

Tube SN74AC10D

AC10

SOIC − D

Tape and reel SN74AC10DR

AC10

−40°C to 85°C

SOP − NS Tape and reel SN74AC10NSR AC10

−40 C to 85 C

SSOP − DB Tape and reel SN74AC10DBR AC10

TSSOP − PW

Tube SN74AC10PW

AC10

TSSOP − PW

Tape and reel SN74AC10PWR

AC10

CDIP − J Tube SNJ54AC10J SNJ54AC10J

−55°C to 125°C

CFP − W Tube SNJ54AC10W SNJ54AC10W

−55 C to 125 C

LCCC − FK Tube SNJ54AC10FK SNJ54AC10FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B C

OUTPUT

H H H L

L XX H

X LX H

X X L H

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (20 pages)

PAGE 1
SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 6.5 ns at 5 V SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1B 1A NC VCC 1C VCC 1C 1Y 3A 3B 3C 3Y 2A NC 2B NC 2C 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y NC 3A NC 3B 2Y GND NC 3Y 3C 1A 1B 2A 2B 2C 2Y GND SN54AC10 . . .
PAGE 2
SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 logic diagram, each gate (positive logic) 1A 1B 1C 2A 2B 2C 3A 3B 3C 1 2 13 12 3 4 5 6 11 10 9 8 1Y 2Y 3Y Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) VCC Supply voltage VIH VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL Input voltage Low-level output current ∆t /∆v MAX MIN MAX 2 6 2 6 2.1 2.1 3.15 3.15 3.85 3.85 0 High-level output current IOL MIN 0 Output voltage IOH SN74AC10 VCC = 4.5 V VCC = 5.5 V Low-level input voltage VI VO SN54AC10 0.9 1.35 1.
PAGE 4
SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A, B, or C Y MIN TA = 25°C TYP MAX SN54AC10 SN74AC10 MIN MAX MIN MAX 1.5 6 9.5 1 11 1 10.5 1.5 5.5 8.
PAGE 5
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74AC10DBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DB 14 2000 330.0 16.4 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74AC10DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AC10NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC10DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74AC10DR SOIC D 14 2500 367.0 367.0 38.0 SN74AC10NSR SO NS 14 2000 367.0 367.0 38.0 SN74AC10PWR TSSOP PW 14 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.