Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate OR gate 74AC TSSOP 14

 

   

SCAS528D − AUGUST 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 7.5 ns at 5 V

SN54AC32 ...J OR W PACKAGE

SN74AC32 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

GND

SN54AC32 . . . FK PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

NC − No internal connection

GND

description/ordering information

The ’AC32 devices are quadruple 2-input positive-OR gates. The devices perform the Boolean function

Y = A + B or Y = A

• B in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC32N SN74AC32N

SOIC − D

Tube SN74AC32D

AC32

SOIC − D

Tape and reel SN74AC32DR

AC32

−40°C to 85°C

SOP − NS Tape and reel SN74AC32NSR AC32

−40 C to 85 C

SSOP − DB Tape and reel SN74AC32DBR AC32

TSSOP − PW

Tube SN74AC32PW

AC32

TSSOP − PW

Tape and reel SN74AC32PWR

AC32

CDIP − J Tube SNJ54AC32J SNJ54AC32J

−55°C to 125°C

CFP − W Tube SNJ54AC32W SNJ54AC32W

−55 C to 125 C

LCCC − FK Tube SNJ54AC32FK SNJ54AC32FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

OUTPUT

H X H

X HH

L L L

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (20 pages)

PAGE 1
SCAS528D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 4B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND SN54AC32 . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC SN54AC32 . . . J OR W PACKAGE SN74AC32 . . .
PAGE 2
SCAS528D − AUGUST 1995 − REVISED OCTOBER 2003 logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SCAS528D − AUGUST 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = −50 µA IOH = −12 mA VOH IOH = −24 mA A or B ports SN54AC32 SN74AC32 MIN MIN MAX 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.56 2.4 2.46 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 MAX 3V 0.002 0.1 0.1 0.1 IOL = 50 µA 4.
PAGE 4
SCAS528D − AUGUST 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION TEST S1 tPLH/tPHL Open From Output Under Test CL = 50 pF (see Note A) S1 Open 50% VCC 50% VCC 0V tPHL tPLH 2 × VCC 500 Ω VCC Input (see Note B) In-Phase Output 50% VCC tPLH tPHL 500 Ω Out-of-Phase Output LOAD CIRCUIT VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AC32DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74AC32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AC32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC32DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74AC32DR SOIC D 14 2500 333.2 345.9 28.6 SN74AC32DR SOIC D 14 2500 367.0 367.0 38.0 SN74AC32PWR TSSOP PW 14 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.