Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Inverted SOIC 20

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SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 9 ns at 5 V

D 3-State Inverting Outputs Drive Bus Lines

Directly

D Full Parallel Access for Loading

D Flow-Through Architecture to Optimize

PCB Layout

description/ordering information

The ’AC564 devices are octal D-type

edge-triggered flip-flops that feature inverting

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input,

the Q

outputs are set to the inverse logic levels set

up at the data (D) inputs.

A buffered output-enable (OE

) input places the

eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In

the high-impedance state, the outputs neither

load nor drive the bus lines significantly. The

high-impedance state and increased drive

provide the capability to drive bus lines without

interface or pullup components.

does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC564N SN74AC564N

SOIC − DW

Tube SN74AC564DW

AC564

SOIC − DW

Tape and reel SN74AC564DWR

AC564

−40°C to 85°C

SOP − NS Tape and reel SN74AC564NSR AC564

−40 C to 85 C

SSOP − DB Tape and reel SN74AC564DBR AC564

TSSOP − PW

Tube SN74AC564PW

AC564

TSSOP − PW

Tape and reel SN74AC564PWR

AC564

CDIP − J Tube SNJ54AC564J SNJ54AC564J

−55°C to 125°C

CFP − W Tube SNJ54AC564W SNJ54AC564W

−55 C to 125 C

LCCC − FK Tube SNJ54AC564FK SNJ54AC564FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

GND

CLK

SN54AC564 ...J OR W PACKAGE

SN74AC564 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

CLK

SN54AC564 . . . FK PACKAGE

(TOP VIEW)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (15 pages)

PAGE 1
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 D D SN54AC564 . . . J OR W PACKAGE SN74AC564 . . .
PAGE 2
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 3
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54AC564 VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v MIN MAX 2 6 Input voltage Low-level output current 2 6 3.15 3.15 3.85 3.85 0 High-level output current MAX 2.1 0 Output voltage MIN 2.1 VCC = 4.5 V VCC = 5.
PAGE 4
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock tw Clock frequency tsu th Setup time, data before CLK↑ SN54AC564 MIN 75 Pulse duration, CLK high or low Hold time, data after CLK↑ SN74AC564 MAX MIN 55 MAX 60 UNIT MHz 6 7.5 7 ns 2.5 4.5 3 ns 2 2.
PAGE 5
SCAS551D− NOVEMBER 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input th 50% VCC VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output Control (low-level enabling) VCC Input 5
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AC564DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AC564PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC564DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AC564PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.