Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

SN54AC573, SN74AC573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 9 ns at 5 V

D 3-State Outputs Drive Bus Lines Directly

description/ordering information

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight latches are D-type transparent latches.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D Inputs.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal

logic state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in a bus-organized system without need for

interface or pullup components.

does not affect the internal operations of the

latches. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC573N SN74AC573N

SOIC DW

Tube SN74AC573DW

AC573

SOIC − DW

Tape and reel SN74AC573DWR

AC573

−40°C to 85°C

SOP − NS Tape and reel SN74AC573NSR AC573

40 C

85 C

SSOP − DB Tape and reel SN74AC573DBR AC573

TSSOP PW

Tube SN74AC573PW

AC573

TSSOP − PW

Tape and reel SN74AC573PWR

AC573

CDIP − J Tube SNJ54AC573J SNJ54AC573J

−55°C to 125°C

CFP − W Tube SNJ54AC573W SNJ54AC573W

55 C

125 C

LCCC − FK Tube SNJ54AC573FK SNJ54AC573FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

SN54AC573 ...J OR W PACKAGE

SN74AC573 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

GND

SN54AC573 . . . FK PACKAGE

(TOP VIEW)

Summary of content (16 pages)

PAGE 1
SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 SN54AC573 . . . J OR W PACKAGE SN74AC573 . . .
PAGE 2
SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 3
SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54AC573 VCC Supply voltage VCC = 3 V VIH High-level High level input voltage MIN MAX 2 6 Low-level Low level input voltage VI Input voltage VO Output voltage IOH High-level High level output current IOL Low-level Low level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature MIN MA
PAGE 4
SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ SN54AC573 MAX MIN SN74AC573 MAX MIN MAX UNIT 6 8 7 ns 3.
PAGE 5
SN54AC573, SN74AC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open 500 Ω LOAD CIRCUIT VCC 50% VCC Timing Input 0V tw tsu 3V Input 50% VCC 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VCC Input 50% VCC 50% VCC 0V 50% VCC Out-of-
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AC573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AC573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74AC573NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC573DBR SN74AC573DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74AC573NSR SO NS 20 2000 367.0 367.0 45.0 SN74AC573PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.