Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting TSSOP 20

GND

CLK

SN54AC574 ...J OR W PACKAGE

SN74AC574 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

GND

CLK

SN54AC574 . . . FK PACKAGE

(TOP VIEW)

SN54AC574, SN74AC574

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 8.5 ns at 5 V

D 3-State Outputs Drive Bus Lines Directly

description/ordering information

These 8-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight flip-flops of the ′AC574 devices are

D-type edge-triggered flip-flops. On the positive

transition of the clock (CLK) input, the Q outputs

are set to the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal

logic state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

the increased drive provide the capability to drive

bus lines in a bus-organized system without need

for interface or pullup components.

does not affect internal operations of the

flip-flop. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC574N SN74AC574N

SOIC DW

Tube SN74AC574DW

AC574

SOIC − DW

Tape and reel SN74AC574DWR

AC574

−40°C to 85°C

SOP − NS Tape and reel SN74AC574NSR AC574

40 C

85 C

SSOP − DB Tape and reel SN74AC574DBR AC574

TSSOP PW

Tube SN74AC574PW

AC574

TSSOP − PW

Tape and reel SN74AC574PWR

AC574

CDIP − J Tube SNJ54AC574J SNJ54AC574J

−55°C to 125°C

CFP − W Tube SNJ54AC574W SNJ54AC574W

55 C

125 C

LCCC − FK Tube SNJ54AC574FK SNJ54AC574FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (20 pages)

PAGE 1
SN54AC574, SN74AC574 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003 SN54AC574 . . . J OR W PACKAGE SN74AC574 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 8.
PAGE 2
SN54AC574, SN74AC574 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 3
SN54AC574, SN74AC574 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) VCC Supply voltage VCC = 3 V VIH High-level High level input voltage VIL Low-level Low level input voltage VI Input voltage VO Output voltage IOH High-level High level output current IOL Low-level Low level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature SN54AC574 SN74AC574
PAGE 4
SN54AC574, SN74AC574 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu th SN54AC574 MAX MIN SN74AC574 MAX 75 MIN UNIT MAX 55 60 MHz 6 7.5 7 ns Setup time, data before CLK↑ 2.5 6.5 3 ns Hold time, data after CLK↑ 1.
PAGE 5
SN54AC574, SN74AC574 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open 500 Ω LOAD CIRCUIT VCC 50% VCC Timing Input 0V tw tsu 3V Input 50% VCC 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VCC Input 50% VCC 50% VCC 0V 50% VCC tPHL O
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AC574DBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AC574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74AC574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC574DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AC574DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AC574PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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