Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74AC SOIC 14

 

   

SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 9 ns at 5 V

SN54AC86 ... J OR W PACKAGE

SN74AC86 ... D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

GND

3 2 1 20 19

910111213

SN54AC86 . . . FK PACKAGE

(TOP VIEW)

GND

NC − No internal connection

description/ordering information

The ’AC86 devices are quadruple 2-input exclusive-OR gates. The devices perform the Boolean function

Y = A  B or Y = A

B + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced

in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the

output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC86N SN74AC86N

SOIC − D

Tube SN74AC86D

AC86

SOIC − D

Tape and reel SN74AC86DR

AC86

−40°C to 85°C

SOP − NS Tape and reel SN74AC86NSR AC86

−40 C to 85 C

SSOP − DB Tape and reel SN74AC86DBR AC86

TSSOP − PW

Tube SN74AC86PW

AC86

TSSOP − PW

Tape and reel SN74AC86PWR

AC86

CDIP − J Tube SNJ54AC86J SNJ54AC86J

−55°C to 125°C

CFP − W Tube SNJ54AC86W SNJ54AC86W

−55 C to 125 C

LCCC − FK Tube SNJ54AC86FK SNJ54AC86FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (21 pages)

PAGE 1
SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 9 ns at 5 V SN54AC86 . . . FK PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 6 9 8 VCC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 7 10 1B 1A NC VCC 4B SN54AC86 . . . J OR W PACKAGE SN74AC86 . . .
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SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003 FUNCTION TABLE (each gate) INPUTS A OUTPUT Y B L L L L H H H L H H H L exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These five equivalent exclusive-OR symbols are valid for an ’AC86 gate in positive logic; negation may be shown at any two ports.
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SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v SN54AC86 SN74AC86 MIN MAX MIN MAX 2 6 2 6 2.1 2.1 3.15 3.15 3.85 3.85 VCC = 4.5 V VCC = 5.5 V Low-level input voltage Input voltage 0 Output voltage 0 High-level output current Low-level output current 0.9 1.35 1.35 1.
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SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y MIN TA = 25°C TYP MAX SN54AC86 SN74AC86 MIN MAX MIN MAX 2 6.5 11.5 1 14 1.5 12.5 2 6 11.5 1 14 1.5 12.
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SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open TEST S1 tPLH/tPHL Open 500 Ω LOAD CIRCUIT tw 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74AC86DBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DB 14 2000 330.0 16.4 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74AC86DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AC86NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC86DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74AC86DR SOIC D 14 2500 367.0 367.0 38.0 SN74AC86NSR SO NS 14 2000 367.0 367.0 38.0 SN74AC86PWR TSSOP PW 14 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.