Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 4.5-V to 5.5-V V

Operation

D Inputs Accept Voltages to 5.5 V

D Max t

of 9.5 ns at 5 V

D Inputs Are TTL-Voltage Compatible

description/ordering information

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight latches are D-type transparent latches.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in a bus-organized system without need for

interface or pullup components.

does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74ACT573N SN74ACT573N

SOIC DW

Tube SN74ACT573DW

ACT573

40°Cto85°C

SOIC − DW

Tape and reel SN74ACT573DWR

ACT573

−40°C to 85°C

SOP − NS Tape and reel SN74ACT573NSR ACT573

SSOP − DB Tape and reel SN74ACT573DBR AD573

TSSOP − PW Tape and reel SN74ACT573PWR AD573

CDIP − J Tube SNJ54ACT573J SNJ54ACT573J

−55°C to 125°C

CFP − W Tube SNJ54ACT573W SNJ54ACT573W

55 C

125 C

LCCC − FK Tube SNJ54ACT573FK SNJ54ACT573FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

SN54ACT573 ...J OR W PACKAGE

SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54ACT573 . . . FK PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (20 pages)

PAGE 1
SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002 SN54ACT573 . . . J OR W PACKAGE SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 9.
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SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) 1 OE LE 11 C1 1D 19 1Q 2 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002 recommended operating conditions (see Note 3) SN54ACT573 SN74ACT573 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.
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SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) D Q LE Q OE Q OE Q TA = 25°C SN54ACT573 SN74ACT573 MIN TYP MAX MIN MAX MIN MAX 2.5 6 10.5 1.5 13.5 2 12 2.5 6 10.5 1.5 13.5 2 12 3 6 10.
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SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open 3V 1.5 V Timing Input LOAD CIRCUIT 0V th tsu 3V 1.5 V Data Input tw 0V 3V 1.5 V Input 1.5 V VOLTAGE WAVEFORMS 1.5 V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ACT573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74ACT573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74ACT573NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ACT573DBR SN74ACT573DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74ACT573NSR SO NS 20 2000 367.0 367.0 45.0 SN74ACT573PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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