Datasheet

 
   
   
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D 4.5-V to 5.5-V V
CC
Operation
D Inputs Accept Voltages to 5.5 V
D Max t
pd
of 10.5 ns at 5 V
D Inputs Are TTL-Voltage Compatible
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
SN54ACT74 ...FK PACKAGE
(TOP VIEW)
1D
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
CC
SN54ACT74 ...J OR W PACKAGE
SN74ACT74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
description/ordering information
The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE
) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE
and CLR are inactive (high), data at the data (D) input meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at D can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube SN74ACT74N SN74ACT74N
SOIC − D
Tube SN74ACT74D
ACT74
SOIC − D
Tape and reel SN74ACT74DR
ACT74
−40°C to 85°C
SOP − NS Tape and reel SN74ACT74NSR ACT74
−40 C to 85 C
SSOP − DB Tape and reel SN74ACT74DBR AD74
TSSOP − PW
Tube SN74ACT74PW
AD74
TSSOP − PW
Tape and reel SN74ACT74PWR
AD74
CDIP − J Tube SNJ54ACT74J SNJ54ACT74J
−55°C to 125°C
CFP − W Tube SNJ54ACT74W SNJ54ACT74W
−55 C to 125 C
LCCC − FK Tube SNJ54ACT74FK SNJ54ACT74FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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