Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NOR gate 74AHC TSSOP 14

SN54AHC02, SN74AHC02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS254K− DECEMBER 1995 − REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 Operating Range 2-V to 5.5-V V

 Latch-Up Performance Exceeds 250 mA Per

JESD 17

 ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

GND

SN54AHC02 ...J OR W PACKAGE

SN74AHC02 . . . D, DB, DGV, N, NS

OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54AHC02 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SN74AHC02 . . . RGY PACKAGE

(TOP VIEW)

114

GND

description/ordering information

The ’AHC02 devices contain four independent 2-input NOR gates that perform the Boolean function

Y = A

 B or Y = A + B in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74AHC02RGYR HA02

PDIP − N Tube SN74AHC02N SN74AHC02N

SOIC D

Tube SN74AHC02D

AHC02

SOIC − D

Tape and reel SN74AHC02DR

AHC02

−40°C to 85°C

SOP − NS Tape and reel SN74AHC02NSR AHC02

SSOP − DB Tape and reel SN74AHC02DBR HA02

TSSOP PW

Tube SN74AHC02PW

HA02

TSSOP − PW

Tape and reel SN74AHC02PWR

HA02

TVSOP − DGV Tape and reel SN74AHC02DGVR HA02

CDIP − J Tube SNJ54AHC02J SNJ54AHC02J

−55°C to 125°C

CFP − W Tube SNJ54AHC02W SNJ54AHC02W

55 C

125 C

LCCC − FK Tube SNJ54AHC02FK SNJ54AHC02FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
SN54AHC02, SN74AHC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS254K− DECEMBER 1995 − REVISED JULY 2003 Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 13 3 12 4 5 6 7 11 10 9 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC 1 2 13 4Y 3 12 4B 4 11 4A 5 10 3Y 9 3B 6 7 8 SN54AHC02 . . .
PAGE 2
SN54AHC02, SN74AHC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS254K− DECEMBER 1995 − REVISED JULY 2003 FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H X L X H L L L H logic diagram (positive logic) 1A 1B 2A 2B 2 1 3 5 6 1Y 3A 3B 4 2Y 4A 4B 8 10 9 11 12 13 3Y 4Y Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Supply voltage range, VCC . . . . . . . . . . .
PAGE 3
SN54AHC02, SN74AHC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS254K− DECEMBER 1995 − REVISED JULY 2003 recommended operating conditions (see Note 4) SN54AHC02 VCC Supply voltage VCC = 2 V VIH MAX 2 5.5 1.5 VCC = 3 V High-level High level input voltage MIN VCC = 5.5 V Input voltage VO Output voltage High-level High level output current IOL Low-level Low level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature 5.5 2.1 0.5 0.5 0.9 0.9 1.65 1.
PAGE 4
SN54AHC02, SN74AHC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS254K− DECEMBER 1995 − REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL ∗ FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A or B Y CL = 15 pF A or B Y CL = 50 pF TA = 25°C MIN SN54AHC02 SN74AHC02 TYP MAX MIN MAX MIN MAX 5.6* 7.9* 1* 9.5* 1 9.5 5.6* 7.9* 1* 9.5* 1 9.5 8.1 11.
PAGE 5
SN54AHC02, SN74AHC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS254K− DECEMBER 1995 − REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC 50% VCC Input 0V th VCC 50% VCC Data Input
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-May-2013 Status (1) SNJ54AHC02W Package Type Package Pins Package Drawing Qty ACTIVE CFP W 14 1 Eco Plan Lead/Ball Finish (2) TBD MSL Peak Temp Op Temp (°C) Top-Side Markings (3) A42 N / A for Pkg Type (4) -55 to 125 5962-9752801QD A SNJ54AHC02W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AHC02DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74AHC02DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74AHC02DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC02DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74AHC02DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74AHC02DR SOIC D 14 2500 367.0 367.0 38.0 SN74AHC02NSR SO NS 14 2000 367.0 367.0 38.0 SN74AHC02PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74AHC02RGYR VQFN RGY 14 3000 367.0 367.0 35.
PAGE 12
PAGE 13
PAGE 14
PAGE 15
PAGE 16
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 17
PAGE 18
PAGE 19
PAGE 20
PAGE 21
PAGE 22
PAGE 23
PAGE 24
PAGE 25
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 26
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.