Datasheet

1
1OE
2
1A 1Y
3
4
2OE
5
2A 2Y
6
10
3OE
9
3A 3Y
8
13
4OE
12
4A 4Y
11
SN74AHC125 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN54AHC125 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1A
1OE
NC
3Y
3A
V
4OE
2Y
GND
NC
CC
NC − No internal connection
SN74AHC125 . . . RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1OE
3Y
V
GND
CC
SN54AHC125 . . . J OR W PACKAGE
SN54AHC125
SN74AHC125
www.ti.com
SCLS256K DECEMBER 1995REVISED JUNE 2013
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Check for Samples: SN54AHC125, SN74AHC125
1
FEATURES
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Operating Range 2-V to 5.5-V
DESCRIPTION
The ’AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(EACH BUFFER)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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