Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74AHC PDIP 14

SN54AHC132, SN74AHC132

QUADRUPLE POSITIVE-NAND GATES

WITH SCHMITT-TRIGGER INPUTS

SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Operating Range 2-V to 5.5-V V

Operation From Very Slow Input

Transitions

Temperature-Compensated Threshold

Levels

High Noise Immunity

Same Pinouts as ’AHC00

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

SN54AHC132 ...J OR W PACKAGE

SN74AHC132 . . . D, DB, DGV, N, NS,

OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54AHC132 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

GND

SN74AHC132 . . . RGY PACKAGE

(TOP VIEW)

114

GND

description/ordering information

The ’AHC132 devices are quadruple positive-NAND gates designed for 2-V to 5.5-V V

operation.

These devices perform the Boolean function Y = A

• B or Y = A + B in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN – RGY Tape and reel SN74AHC132RGYR HA132

PDIP – N Tube SN74AHC132N SN74AHC132N

SOIC – D

Tube SN74AHC132D

AHC132

–40

Cto85

SOIC

–

Tape and reel SN74AHC132DR

AHC132

–

40°C

85°C

SOP – NS Tape and reel SN74AHC132NSR AHC132

SSOP – DB Tape and reel SN74AHC132DBR HA132

TSSOP – PW Tape and reel SN74AHC132PWR HA132

TVSOP – DGV Tape and reel SN74AHC132DGVR HA132

CDIP – J Tube SNJ54AHC132J SNJ54AHC132J

–55°C to 125°C

CFP – W Tube SNJ54AHC132W SNJ54AHC132W

LCCC – FK Tube SNJ54AHC132FK SNJ54AHC132FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (11 pages)

PAGE 1
SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 1Y NC 2A NC 2B 13 4B 2 3 12 4A 4 11 4Y 10 3B 9 3A 5 6 7 8 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1 SN54AHC132 . . .
PAGE 2
SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 description/ordering information (continued) Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
PAGE 3
SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 recommended operating conditions (see Note 4) SN54AHC132 SN74AHC132 MIN MAX MIN MAX UNIT VCC VI Supply voltage 2 5.5 2 5.5 V Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC –50 0 VCC –50 mA IOH VCC = 2 V VCC = 3.3 V ± 0.3 V High-level output current VCC = 5 V ± 0.5 V VCC = 2 V IOL VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.
PAGE 4
SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC132 SN74AHC132 MIN MAX MIN MAX 5.6* 11.9* 1* 14* 1 14 5.6* 11.
PAGE 5
SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 23-May-2011 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AHC132DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74AHC132DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74AHC132DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC132DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74AHC132DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74AHC132DR SOIC D 14 2500 367.0 367.0 38.0 SN74AHC132NSR SO NS 14 2000 367.0 367.0 38.0 SN74AHC132PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74AHC132RGYR VQFN RGY 14 3000 367.0 367.0 35.
PAGE 11
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.