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SN54AHC16240, SN74AHC16240

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCLS326G – MARCH 1996 – REVISED JANUARY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

Widebus

 Family

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

Operating Range 2-V to 5.5-V V

Distributed V

and GND Pins Minimize

High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’AHC16240 devices are 16-bit buffers and

line drivers designed specifically to improve the

performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented

receivers and transmitters.

These devices can be used as four 4-bit buffers,

two 8-bit buffers, or one 16-bit buffer. They provide

inverting outputs and symmetrical active-low

output-enable (OE

) inputs.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHC16240 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74AHC16240 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 4-bit buffer/driver)

INPUTS

OUTPUT

OE A

L H L

L LH

H X Z

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

SN54AHC16240 . . . WD PACKAGE

SN74AHC16240 . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1OE

1Y1

1Y2

GND

1Y3

1Y4

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

4A1

4A2

GND

4A3

4A4

3OE

Summary of content (14 pages)

PAGE 1
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS326G – MARCH 1996 – REVISED JANUARY 2000 D D D D D D D SN54AHC16240 . . . WD PACKAGE SN74AHC16240 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.
PAGE 2
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS326G – MARCH 1996 – REVISED JANUARY 2000 logic symbol† 1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1 EN1 48 25 24 EN2 EN3 EN4 47 1 1 46 3 44 5 43 6 41 8 1 2 40 9 38 11 37 12 36 1 3 13 35 14 33 16 32 17 30 19 1 4 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS326G – MARCH 1996 – REVISED JANUARY 2000 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-ai
PAGE 4
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS326G – MARCH 1996 – REVISED JANUARY 2000 recommended operating conditions (see Note 3) SN54AHC16240 VCC VIH Supply voltage VCC = 2 V VCC = 3 V High-level input voltage Low-level input voltage VI VO 2 5.5 Output voltage ∆t/∆v 5.5 2.1 V V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC –50 0 VCC –50 mA VCC = 3.3 ± 0.3 V VCC = 5 ± 0.5 V VCC = 3.3 ± 0.3 V Input transition rise or fall rate 2 UNIT 1.5 3.
PAGE 5
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS326G – MARCH 1996 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.
PAGE 6
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS326G – MARCH 1996 – REVISED JANUARY 2000 noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHC16240 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.6 V Quiet output, minimum dynamic VOL –0.6 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.6 V High-level dynamic input voltage 3.
PAGE 7
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS326G – MARCH 1996 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VC
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AHC16240DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74AHC16240DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC16240DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74AHC16240DGVR TVSOP DGV 48 2000 346.0 346.0 33.
PAGE 11
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 12
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 13
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 14
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