Datasheet

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SN54AHC16540, SN74AHC16540

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCLS331F – MARCH 1996 – REVISED JANUARY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

Widebus

 Family

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

Operating Range 2-V to 5.5-V V

Distributed V

and GND Pins Minimize

High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

These 16-bit buffers and bus drivers provide a

high-performance bus interface for wide data

paths.

The 3-state control gate is a 2-input AND gate with

active-low inputs so that if either output-enable

(OE1

or OE2) input is high, all corresponding

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHC16540 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74AHC16540 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 8-bit buffer/driver)

INPUTS

OUTPUT

OE1 OE2

L L L H

L LH L

H XX Z

X H X Z

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

SN54AHC16540 . . . WD PACKAGE

SN74AHC16540 . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1OE1

1Y1

1Y2

GND

1Y3

1Y4

1Y5

1Y6

GND

1Y7

1Y8

2Y1

2Y2

GND

2Y3

2Y4

2Y5

2Y6

GND

2Y7

2Y8

2OE1

1OE2

1A1

1A2

GND

1A3

1A4

1A5

1A6

GND

1A7

1A8

2A1

2A2

GND

2A3

2A4

2A5

2A6

GND

2A7

2A8

2OE2

Summary of content (13 pages)

PAGE 1
SN54AHC16540, SN74AHC16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS331F – MARCH 1996 – REVISED JANUARY 2000 D D D D D D D D SN54AHC16540 . . . WD PACKAGE SN74AHC16540 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.
PAGE 2
SN54AHC16540, SN74AHC16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS331F – MARCH 1996 – REVISED JANUARY 2000 logic symbol† 1OE1 1 & 48 EN1 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 24 & EN2 25 47 1 46 2 1 3 44 5 43 6 41 8 40 9 38 11 37 12 13 36 1 35 2 14 33 16 32 17 30 19 29 20 27 22 26 23 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC P
PAGE 3
SN54AHC16540, SN74AHC16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS331F – MARCH 1996 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 4
SN54AHC16540, SN74AHC16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS331F – MARCH 1996 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 mA VOH IOH = –4 mA IOH = –8 mA IOL = 50 mA VOL IOL = 4 mA IOL = 8 mA II IOZ ICC Ci VI = VCC or GND VO = VCC or GND, VI (OE) = VIL or VIH VI = VCC or GND, VI = VCC or GND MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.
PAGE 5
SN54AHC16540, SN74AHC16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS331F – MARCH 1996 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.
PAGE 6
SN54AHC16540, SN74AHC16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS331F – MARCH 1996 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VC
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AHC16540DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74AHC16540DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC16540DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74AHC16540DGVR TVSOP DGV 48 2000 346.0 346.0 33.
PAGE 10
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 11
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 12
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 13
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