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ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SC 70 5
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SCLS379J − AUGUST 1997 − REVISED JUNE 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Operating Range of 2 V to 5.5 V
D Max t
pd
of 6 ns at 5 V
D Low Power Consumption, 10-µA Max I
CC
D ±8-mA Output Drive at 5 V
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
3
2
4
51
OE V
CC
Y
A
GND
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
51
OE V
CC
Y
A
GND
3
2
4
51
OE V
CC
Y
A
GND
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
description/ordering information
The SN74AHC1G126 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the
output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
SOT (SOT-23) – DBV
Reel of 3000 SN74AHC1G126DBVR
A26_
SOT (SOT-23) – DBV
Reel of 250 SN74AHC1G126DBVT
A26_
−40°C to 85°C
SOT (SC-70) – DCK
Reel of 3000 SN74AHC1G126DCKR
AN_
−40 C to 85 C
SOT (SC-70) – DCK
Reel of 250 SN74AHC1G126DCKT
AN_
SOT (SOT-553) – DRL Reel of 4000 SN74AHC1G126DRLR AN_
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
‡
The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUT
OE A
OUTPUT
Y
H H H
H LL
L X Z
logic diagram (positive logic)
AY
OE
1
24
Copyright 2005, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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