Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state PDIP 20

 

   

  

SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Operating Range 2-V to 5.5-V V

D 3-State Outputs Directly Drive Bus Lines

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

description/ordering information

The ’AHC573 devices are octal transparent

D-type latches designed for 2-V to 5.5-V V

operation.

When the latch-enable (LE) input is high, the

Q outputs follow the data (D) inputs. When LE is

low, the Q outputs are latched at the logic levels

of the D inputs.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal logic

state (high or low) or the high-impedance state. In

the high-impedance state, the outputs neither

load nor drive the bus lines significantly. The

high-impedance state and increased drive

provide the capability to drive bus lines without

interface or pullup components.

does not affect the internal operations of the

latches. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AHC573N SN74AHC573N

SOIC − DW

Tube SN74AHC573DW

AHC573

SOIC − DW

Tape and reel SN74AHC573DWR

AHC573

−40

C to 85

SOP − NS Tape and reel SN74AHC573NSR AHC573

−40

C to 85

SSOP − DB Tape and reel SN74AHC573DBR HA573

TSSOP − PW

Tube SN74AHC573PW

HA573

TSSOP − PW

Tape and reel SN74AHC573PWR

HA573

TVSOP − DGV Tape and reel SN74AHC573DGVR HA573

CDIP − J Tube SNJ54AHC573J SNJ54AHC573J

−55°C to 125°C

CFP − W Tube SNJ54AHC573W SNJ54AHC573W

−55 C to 125 C

LCCC − FK Tube SNJ54AHC573FK SNJ54AHC573FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54AHC573 ...J OR W PACKAGE

SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54AHC573 . . . FK PACKAGE

(TOP VIEW)

GND

3212019

910111213

7Q 1Q

GND

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Summary of content (24 pages)

PAGE 1
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004 D Operating Range 2-V to 5.5-V VCC D 3-State Outputs Directly Drive Bus Lines D Latch-Up Performance Exceeds 250 mA Per SN54AHC573 . . . J OR W PACKAGE SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D GND JESD 17 description/ordering information The ’AHC573 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation.
PAGE 2
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 1D 19 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004 recommended operating conditions (see Note 3) SN54AHC573 VCC VIH Supply voltage VCC = 2 V VCC = 3 V High-level input voltage VI VO IOH MAX 2 5.5 1.5 VCC = 5.5 V VCC = 2 V VIL MIN Output voltage ∆t/∆v 2.1 V V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC −50 0 VCC −50 mA VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.
PAGE 4
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54AHC573 MIN MAX SN74AHC573 MIN MAX UNIT tw Pulse duration, LE high 5 5 5 ns tsu Setup time, data before LE↓ 3.5 3.5 3.5 ns th Hold time, data after LE↓ 1.5 1.5 1.
PAGE 5
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.
PAGE 6
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VC
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74AHC573DBR SSOP DB 20 2000 330.0 16.4 SN74AHC573DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74AHC573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC573DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74AHC573DGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74AHC573DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74AHC573NSR SO NS 20 2000 367.0 367.0 45.0 SN74AHC573PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74AHC573PWR TSSOP PW 20 2000 364.0 364.0 27.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 24
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.