Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Push pull PDIP 16

 

  

  

SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Operating Range 2-V to 5.5-V V

D 8-Bit Serial-In, Parallel-Out Shift

Registers With Storage

D Independent Direct Overriding Clears

on Shift and Storage Registers

D Independent Clocks for Shift and

Storage Registers

D Latch-Up Performance Exceeds 100 mA

Per JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The ’AHC594 devices contain an 8-bit serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. Separate clocks and direct

overriding clear (SRCLR

, RCLR) inputs are

provided on the shift and storage registers. A

serial (Q

H′

) output is provided for cascading

purposes.

The shift register (SRCLK) and storage register

(RCLK) clocks are positive-edge triggered. If the

clocks are tied together, the shift register always

is one clock pulse ahead of the storage register.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AHC594N SN74AHC594N

SOIC − D

Tube SN74AHC594D

AHC594

SOIC − D

Tape and reel SN74AHC594DR

AHC594

−40°C to 85°C

SOP − NS Tape and reel SN74AHC594NSR AHC594

−40 C to 85 C

SSOP − DB Tape and reel SN74AHC594DBR HA594

TSSOP − PW

Tube SN74AHC594PW

HA594

TSSOP − PW

Tape and reel SN74AHC594PWR

HA594

CDIP − J Tube SNJ54AHC594J SNJ54AHC594J

−55°C to 125°C

CFP − W Tube SNJ54AHC594W SNJ54AHC594W

−55 C to 125 C

LCCC − FK Tube SNJ54AHC594FK SNJ54AHC594FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

    !"#$% !%&% 

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)&(&#$$(,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54AHC594 ...J OR W PACKAGE

SN74AHC594 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54AHC594 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

SER

RCLR

RCLK

SRCLK

SRCLR

H′

3212019

91011 1213

SER

RCLR

RCLK

SRCLK

SRCLR

GND

′

Summary of content (21 pages)

PAGE 1
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 D Operating Range 2-V to 5.5-V VCC D 8-Bit Serial-In, Parallel-Out Shift SN54AHC594 . . . J OR W PACKAGE SN74AHC594 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) Registers With Storage D Independent Direct Overriding Clears 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54AHC594 . . .
PAGE 2
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 FUNCTION TABLE INPUTS 2 FUNCTION SER SRCLK SRCLR RCLK RCLR X X L X X Shift register is cleared. L ↑ H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L ↓ H X X Shift register state is not changed.
PAGE 3
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 logic diagram (positive logic) 13 RCLR 12 RCLK 10 SRCLR SRCLK SER 11 14 1D Q C1 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R R 3D Q C3 15 R 3D Q C3 1 R 3D Q C3 2 R 3D Q C3 3 R 3D Q C3 4 R 3D Q C3 5 R 3D Q C3 6 R 3D Q C3 7 QA QB QC QD QE QF QG QH 9 QH′ Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
PAGE 4
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 timing diagram SRCLK SER RCLK SRCLR RCLR QA QB QC QD QE QF QG QH QH′ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAGE 5
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 6
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 3V 2.58 2.48 2.48 3.94 3.8 3.8 IOH = −50 mA VOH IOH = −4 mA QH′, IOH = −4 mA 4.5 V QA−QH, IOH = −8 mA IOL = 50 mA VOL II ICC VI = 5.
PAGE 7
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX RCLK or SRCLK high or low tw tsu Pulse duration Setup time SN54AHC594 MIN MAX SN74AHC594 MIN 5 5 5 RCLR or SRCLR low 5.2 5.2 5.
PAGE 8
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.
PAGE 9
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Da
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74AHC594DBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q1 DB 16 2000 330.0 16.4 8.2 6.6 2.5 SN74AHC594DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74AHC594NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC594DBR SSOP DB 16 2000 367.0 367.0 38.0 SN74AHC594DR SOIC D 16 2500 333.2 345.9 28.6 SN74AHC594NSR SO NS 16 2000 367.0 367.0 38.0 SN74AHC594PWR TSSOP PW 16 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.