Datasheet

SN74AHC595 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHC595 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
C
D
E
F
G
H
Q
Q
Q
Q
Q
Q
Q
GND
V
CC
Q
SER
A
OE
RCLK
SRCLK
SRCLR
Q
H
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
SER
OE
NC
RCLK
SRCLK
Q
Q
NC
D
E
Q
Q
F
G
Q
NC
SRCLR
H
GND
NC
C
Q
B
V
CC
Q
A
Q
H
Q
SN54AHC595 . . . J OR W PACKAGE
SN54AHC595, SN74AHC595
www.ti.com
SCLS373J MAY 1996REVISED JULY 2013
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
Check for Samples: SN54AHC595, SN74AHC595
1
FEATURES
DESCRIPTION
The ’AHC595 devices contain an 8-bit serial-in,
Operating Range 2-V to 5.5-V V
CC
parallel-out shift register that feeds an 8-bit D-type
8-Bit Serial-In, Parallel-Out Shift
storage register. The storage register has parallel 3-
Latch-Up Performance Exceeds 100 mA Per
state outputs. Separate clocks are provided for both
JESD 78, Class II
the shift and storage registers. The shift register has
a direct overriding clear (SRCLR) input, serial (SER)
ESD Protection Exceeds JESD 22
input, and a serial output for cascading. When the
2000-V Human-Body Model (A114-A)
output-enable (OE) input is high, all outputs, except
200-V Machine Model (A115-A)
QH, are in the high-impedance state.
1000-V Charged-Device Model (C101)
Both the shift-register clock (SRCLK) and storage-
register clock (RCLK) are positive-edge triggered. If
both clocks are connected together, the shift register
always is one clock pulse ahead of the storage
register.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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