Datasheet

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SN54AHCT16373, SN74AHCT16373

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCLS336H – MARCH 1996 – REVISED JANUARY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

Widebus

 Family

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

Inputs Are TTL-Voltage Compatible

Distributed V

and GND Pins Minimize

High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’AHCT16373 devices are 16-bit transparent

D-type latches with 3-state outputs designed

specifically for driving highly capacitive or

relatively low-impedance loads. They are

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,

the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up

at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus

lines without need for interface or pullup components.

does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHCT16373 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74AHCT16373 is characterized for operation from –40°C to 85°C.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

SN54AHCT16373 . . . WD PACKAGE

SN74AHCT16373 . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1LE

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2LE

Summary of content (13 pages)

PAGE 1
SN54AHCT16373, SN74AHCT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS336H – MARCH 1996 – REVISED JANUARY 2000 D D D D D D D D Members of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds
PAGE 2
SN54AHCT16373, SN74AHCT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS336H – MARCH 1996 – REVISED JANUARY 2000 FUNCTION TABLE (each 8-bit latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C3 24 2EN 25 C4 47 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q2
PAGE 3
SN54AHCT16373, SN74AHCT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS336H – MARCH 1996 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SN54AHCT16373, SN74AHCT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS336H – MARCH 1996 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH IOH = –50 mA IOH = –8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 II IOZ VI = VCC or GND VO = VCC or GND ICC VI = VCC or GND, IO = 0 One input at 3.
PAGE 5
SN54AHCT16373, SN74AHCT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS336H – MARCH 1996 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.
PAGE 6
SN54AHCT16373, SN74AHCT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS336H – MARCH 1996 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.8 1.8 12.0 24.0 Q1 SN74AHCT16373DGGR TSSOP DGG 48 2000 330.0 24.4 SN74AHCT16373DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74AHCT16373DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHCT16373DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74AHCT16373DGVR TVSOP DGV 48 2000 346.0 346.0 33.0 SN74AHCT16373DLR SSOP DL 48 1000 346.0 346.0 49.
PAGE 10
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 11
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 12
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 13
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