Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate AND gate 74ALS PDIP 14

SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11

TRIPLE 3-INPUT POSITIVE-AND GATES

SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.5-V to 5.5-V V

Operation

Max t

of 5.5 ns at 5 V

SN54ALS11A, ...J OR W PACKAGE

SN54AS11 ...J PACKAGE

SN74ALS11A, SN74AS11 . . . D, N, OR NS PACKAGE

(TOP VIEW)

GND

SN54ALS11A, SN54AS11 . . . FK PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

NC – No internal connection

GND

description/ordering information

These devices contain three independent 3-input positive-AND gates. They perform the Boolean functions

Y A • B • CorY A

B C

in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP N

Tube

SN74ALS11AN SN74ALS11AN

PDIP

–

Tube

SN74AS11N SN74AS11N

Tube SN74ALS11AD

ALS11A

0°Cto70°C

SOIC D

Tape and reel SN74ALS11ADR

ALS11A

0°C

70°C

SOIC

–

Tube SN74AS11D

AS11

Tape and reel SN74AS11DR

AS11

SOP NS

e and reel

SN74ALS11ANSR ALS11A

SOP

–

Tape

and

reel

SN74AS11NSR 74AS11

CDIP J

Tube

SNJ54ALS11AJ SNJ54ALS11AJ

CDIP

–

Tube

SNJ54AS11J SNJ54AS11J

–55°C to 125°C

CFP – W Tube SNJ54ALS11AW SNJ54ALS11AW

LCCC FK

Tube

SNJ54ALS11AFK SNJ54ALS11AFK

LCCC

–

Tube

SNJ54AS11FK SNJ54AS11FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (19 pages)

PAGE 1
SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 4.5-V to 5.5-V VCC Operation Max tpd of 5.5 ns at 5 V SN54ALS11A, . . . J OR W PACKAGE SN54AS11 . . . J PACKAGE SN74ALS11A, SN74AS11 . . .
PAGE 2
SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 FUNCTION TABLE (each gate) INPUTS A B C OUTPUT Y H H H H L X X L X L X L X X L L logic diagram, each gate (positive logic) 1A 1B 1C 2A 2B 2C 3A 3B 3C 1 2 13 12 3 4 5 6 9 10 11 8 1Y 2Y 3Y Pin numbers shown are for the D, J, N, NS, and W packages.
PAGE 3
SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54ALS11A TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –0.4 mA VOL 5V VCC = 4 4.5 IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.
PAGE 4
SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 recommended operating conditions (see Note 2) SN54AS11 SN74AS11 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.
PAGE 5
SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALS11ADR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ALS11ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74AS11DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS11ADR SOIC D 14 2500 367.0 367.0 38.0 SN74ALS11ANSR SO NS 14 2000 367.0 367.0 38.0 SN74AS11DR SOIC D 14 2500 367.0 367.0 38.0 SN74AS11NSR SO NS 14 2000 367.0 367.0 38.
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