Datasheet
SDAS159D − APRIL 1982 − REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
• AND-Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Direct Clear
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
description
This 8-bit parallel-out serial shift register features
AND-gated serial (A and B) inputs and an
asynchronous clear (CLR
) input. The gated serial
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
†
CLR CLK A B Q
A
Q
B
...Q
H
L X X X L L L
H LXXQ
A0
Q
B0
Q
H0
H ↑ HHHQ
An
Q
Gn
H ↑ LXLQ
An
Q
Gn
H ↑ X L L Q
An
Q
Gn
†
Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
, or Q
H
, respectively,
before the indicated steady-state input conditions were
established.
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
↑ = transition from low to high level
Q
An
, Q
Gn
= the level of Q
A
or Q
G
before the most recent
↑ transition of the clock; indicates a 1-bit shift.
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
Q
A
Q
B
Q
C
Q
D
GND
V
CC
Q
H
Q
G
Q
F
Q
E
CLR
CLK
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