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ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74ALS Positive slope 30 MHz PDIP 16
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 
    
SDAS210C − DECEMBER 1982 − REVISED JULY 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
D Single Down/Up Count-Control Line
D Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
D Fully Synchronous in Count Modes
D Asynchronously Presettable With Load
Control
D Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’ALS191A are synchronous 4-bit reversible
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincidentally with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count enable (CTEN
) input is low. A
high at CTEN
inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U
) input. When D/U is low, the counter
counts up, and when D/U
is high, the counter
counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN
and D/U) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter is dictated solely by the conditions meeting the stable setup and hold times.
These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD
input and entering the desired data at the data inputs. The output changes to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
CLK, D/U
, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on
(current required by) clock drivers, for long parallel words.
Copyright 1996, Texas Instruments Incorporated
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
GND
V
CC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54ALS191A ...J PACKAGE
SN74ALS191A ...D OR N PACKAGE
(TOP VIEW)
SN54ALS191A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
CLK
RCO
NC
MAX/MIN
LOAD
Q
A
CTEN
NC
D/U
Q
C
B
NC
D
C
A
Q
GND
NC
D
Q
B
V
CC
NC − No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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