Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch D type, Addressable Standard SOIC 16 N

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SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• 8-Bit Parallel-Out Storage Register

Performs Serial-to-Parallel Conversion With

Storage

• Asynchronous Parallel Clear

• Active-High Decoder

• Enable/Disable Input Simplifies Expansion

• Expandable for n-Bit Applications

• Four Distinct Functional Modes

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These 8-bit addressable latches are designed for

general-purpose storage applications in digital

systems. Specific uses include working registers,

serial-holding registers, and active-high decoders

or demultiplexers. They are multifunctional

devices capable of storing single-line data in eight

addressable latches and being a 1-of-8 decoder or

demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by

controlling the clear (CLR

) and enable (G) inputs

as shown in the function table. In the

addressable-latch mode, data at the data-in

terminal is written into the addressed latch. The

addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the

memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To

eliminate the possibility of entering erroneous data in the latches, G

should be held high (inactive) while the

address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the

level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address

and data inputs.

The SN54ALS259 is characterized for operation over the full military temperature range of −55°C to 125°C. The

SN74ALS259 is characterized for operation from 0°C to 70°C.

Function Tables

FUNCTION

INPUTS

OUTPUT OF

ADDRESSED

EACH

OTHER

FUNCTION

CLR G

ADDRESSED

LATCH

OTHER

OUTPUT

FUNCTION

H L D Q

Addressable latch

H HQ

Memory

L LD L 8-line demultiplexer

L H L L Clear

D = the level at the data input.

= the level of Q

(i = Q, 1,...7 as appropriate) before the indicated

steady-state input conditions were established.

SN54ALS259 ...J PACKAGE

SN74ALS259 ...D OR N PACKAGE

(TOP VIEW)

3212019

910111213

SN54ALS259 . . . FK PACKAGE

(TOP VIEW)

CLR

GND

NC − No internal connection

GND

CLR

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Summary of content (17 pages)

PAGE 1
SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994 • • • • • • • SN54ALS259 . . . J PACKAGE SN74ALS259 . . .
PAGE 2
SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994 Function Tables (Continued) LATCH SELECTION SELECT INPUTS S2 S1 S0 LATCH ADDRESSED L L L 0 L L H 1 L H L 2 L H H 3 H L L 4 H L H 5 H H L 6 H H H 7 logic symbol† S0 S1 S2 1 3 14 G D CLR 0 2 13 15 8M 0 7 2 G8 Z9 Z10 4 9, 0D 10, 0R 5 9, 1D 10, 1R 6 9, 2D 10, 2R 7 9, 3D 10, 3R 9 9, 4D 10, 4R 10 9, 5D 10, 5R 11 9, 6D 10, 6R 12 9, 7D 10, 7R † This symbol is
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SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994 logic diagram (positive logic) G D 14 4 13 5 S0 7 10 Q3 Q4 Q5 3 11 12 CLR Q2 2 9 S2 Q1 1 6 S1 Q0 Q6 Q7 15 Pin numbers shown are for the D, J, and N packages.
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SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.
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SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point From Output Under Test LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALS259DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.5 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS259DR SOIC D 16 2500 333.2 345.9 28.
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