Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

GND

DW OR N PACKAGE

(TOP VIEW)

SN74ALS533A, SN74AS533A

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SDAS270 – DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Eight Latches in a Single Package

• 3-State Bus-Driving Inverting Outputs

• Full Parallel Access for Loading

• Buffered Control Inputs

• pnp Inputs Reduce dc Loading on

Data Lines

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard

Plastic (N) 300-mil DIPs

description

These 8-bit D-type transparent latches feature

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While latch-enable (LE) input is high, the Q

outputs follow the complements of the data (D) inputs. When LE is

taken low, the Q

outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and

SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted

outputs.

A buffered output-enable (OE

) input places the eight outputs in either a normal logic state (high or low logic

levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the capability to drive bus lines without

interface or pullup components.

does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are off.

The SN74ALS533A and SN74AS533A are characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE LE D

L H H L

L HL H

LLX Q

HXX Z

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (15 pages)

PAGE 1
SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 • • • • • • DW OR N PACKAGE (TOP VIEW) Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading Buffered Control Inputs pnp Inputs Reduce dc Loading on Data Lines Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8
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SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 logic symbol† 1 OE LE 1D 2D 3D 4D 5D 6D 7D 8D 11 3 4 logic diagram (positive logic) OE EN LE C1 1D 1 2 5 7 6 8 9 13 12 14 15 17 16 18 1 19 11 C1 1Q 1D 3 2 1Q 1D 2Q 3Q 4Q C1 2D 4 5Q C1 8Q 3D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 recommended operating conditions SN74ALS533A MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage High-level output current – 2.6 mA IOL tw Low-level output current 24 mA Pulse duration, LE high 15 ns tsu th Setup time, data before LE↓ 15 ns Hold time, data after LE↓ 7 ns TA Operating free-air temperature 0 High-level input voltage 2 V V 0.
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SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.
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SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IO‡ ICC SN74AS533A TYP† MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4.5 V, VCC = 4.5 V, IOH = – 15 mA IOL = 48 mA VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V VCC = 5.5 V, VCC = 5.
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SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALS533ANSR Package Package Pins Type Drawing SO NS 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.5 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS533ANSR SO NS 20 2000 367.0 367.0 45.
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