Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

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SDAS048D − DECEMBER 1989 − REVISED JANUARY 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• 3-State Buffer-Type Outputs Drive Bus

Lines Directly

• Bus-Structured Pinout

• True Logic Outputs

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), Standard Plastic (N) and

Ceramic (J) 300-mil DIPs, and Ceramic Flat

(W) Packages

description

These octal D-type transparent latches feature

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, outputs

(Q) respond to the data (D) inputs. When LE is low,

the outputs are latched to retain the data that was

set up.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal logic

state (high or low) or a high-impedance state. In

the high-impedance state, the outputs neither load

nor drive the bus lines significantly. The

high-impedance state and the increased drive

provide the capability to drive bus lines without

interface or pullup components.

does not affect internal operation of the

latches. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range

of −55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE LE D

OUTPUT

L H H H

L HL L

L LX Q

H X X Z

GND

SN54ALS573C, SN54AS573A...J OR W PACKAGE

SN74ALS573C, SN74AS573A...DW OR N PACKAGE

(TOP VIEW)

3212019

910111213

SN54ALS573C, SN54AS573A...FK PACKAGE

(TOP VIEW)

7Q 1Q

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Summary of content (21 pages)

PAGE 1
SDAS048D − DECEMBER 1989 − REVISED JANUARY 1995 OE 1D 2D 3D 4D 5D 6D 7D 8D GND description These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
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logic symbol† logic diagram (positive logic) SDAS048D − DECEMBER 1989 − REVISED JANUARY 1995 OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 EN OE C1 19 1D 3 18 4 17 5 16 6 15 7 14 8 13 9 12 LE 1 11 1Q C1 2Q 1D 3Q 2 19 1Q 1D 4Q 5Q 6Q 7Q To Seven Other Channels 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SDAS048D − DECEMBER 1989 − REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK SN54ALS573C TYP† MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = − 18 mA IOH = − 0.4 mA VCC = 4.5 V IOH = − 1 mA IOH = − 2.6 mA VOL VCC = 4.5 V IOL = 12 mA IOL = 24 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.
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SDAS048D − DECEMBER 1989 − REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SDAS048D − DECEMBER 1989 − REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† SN54AS573A SN74AS573A MIN MAX MIN MAX 3 11 3 8 3 8 3 7 6 16.5 6 13 4 9 4 7.5 2 8 2 6.5 4 11 4 9.5 2 8 2 6.
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SDAS048D − DECEMBER 1989 − REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS 3.5 V High-Level Pulse 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Sep-2013 Status (1) Package Type Package Pins Package Drawing Qty SNJ54AS573AFK OBSOLETE LCCC FK 20 SNJ54AS573AJ ACTIVE CDIP J 20 1 Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TBD Call TI Call TI -55 to 125 TBD A42 N / A for Pkg Type -55 to 125 SNJ54AS573AJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALS573CDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74ALS573CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74ALS573CNSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS573CDBR SSOP DB 20 2000 367.0 367.0 38.0 SN74ALS573CDWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS573CNSR SO NS 20 2000 367.0 367.0 45.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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