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SN74ALS992

9-BIT D-TYPE TRANSPARENT READ-BACK LATCH

WITH 3-STATE OUTPUTS

SDAS028B – APRIL 1984 – REVISED JANUARY 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• 3-State I/O-Type Read-Back Inputs

• Bus-Structured Pinout

• True Logic Outputs

• Designed With Nine Bits for Parity

Applications

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard

Plastic (NT) 300-mil DIPs

description

This 9-bit latch is designed specifically for storing

the contents of the input data bus and providing

the capability of reading back the stored data onto

the input data bus. In addition, this device provides

a 3-state buffer-type output and is easily

implemented in parity applications.

The nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow

the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable (OEQ

) input is high.

Read back is provided through the output-enable (OERB

) input. When OERB is taken low, the data present at

the output of the data latches is allowed to pass back onto the input data bus. When OERB

is taken high, the

output of the data latches is isolated from the D inputs. OERB

does not affect the internal operation of the latches;

however, precautions should be taken not to create a bus conflict.

The SN74ALS992 is characterized for operation from 0°C to 70°C.

logic symbol

†

CLR

EN2

OERB

EN3

OEQ

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

DW OR NT PACKAGE

(TOP VIEW)

OERB

CLR

GND

OEQ

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (9 pages)

PAGE 1
SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE (TOP VIEW) 3-State I/O-Type Read-Back Inputs Bus-Structured Pinout True Logic Outputs Designed With Nine Bits for Parity Applications Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs OERB 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND description This 9-bit latch is designed specifically for storing the contents of the inp
PAGE 2
SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 logic diagram (positive logic) OEQ OERB CLR LE 1D 14 1 11 13 2 23 1D 1Q C1 R To Eight Other Channels timing diagram Data Bus Input Data tsu Read Back Input Data th LE tsu† tdis OERB tpd tpd Q CLR = H, OEQ = L † This setup time ensures that the read-back circuit will not create a conflict on the input data bus.
PAGE 3
SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 recommended operating conditions MIN NOM MAX 4.5 5 5.5 VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level tw Pulse duration tsu Setup time th TA Hold time, data after LE↓ 5 Operating free-air temperature 0 High-level input voltage 2 Q – 2.6 D – 0.
PAGE 4
SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM ((INPUT)) TO (OUTPUT) ( ) VCC = 4.5 V to 5.
PAGE 5
SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V 7V S1 S1 500 Ω 1 kΩ Test Point From Output Under Test CL (see Note A) CL (see Note A) 500 Ω LOAD CIRCUIT FOR Q OUTPUTS 1 kΩ LOAD CIRCUIT FOR D OUTPUTS 3.5 V Timing Input Test Point From Output Under Test 1.3 V 3.5 V High-Level Pulse 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 1.3 V 0.
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PACKAGE OPTION ADDENDUM www.ti.
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