Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 24

SN54ALS996 . . . JT PACKAGE

SN74ALS996 . . . DW OR NT PACKAGE

(TOP VIEW)

SN54ALS996 . . . FK PACKAGE

(TOP VIEW)

CLK

GND

T/C

CLR

NC − No internal connection

3212827

12 13

426

14 15 16 17 18

CLK

GND

CLR

T/C

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SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995

2−1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• 3-State I/O-Type Read-Back Inputs

• Bus-Structured Pinout

• T/C Determines True or Complementary

Data at Q Outputs

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

(NT) and Ceramic (JT) 300-mil DIPs

description

These 8-bit latches are designed specifically for

storing the contents of the input data bus and

providing the capability of reading back the stored

data onto the input data bus. The Q outputs are

designed with bus-driving capability.

The edge-triggered flip-flops enter the data on the

low-to-high transition of the clock (CLK) input

when the enable (EN

) input is low. Data can be

read back onto the data inputs by taking the read

(RD

) input low, in addition to having EN low. When

is high, both the read-back and write modes

are disabled. Transitions on EN

should only be

made with CLK high to prevent false clocking.

The polarity of the Q outputs can be controlled by

the polarity (T/C

) input. When T/C is high, Q is the

same as is stored in the flip-flops. When T/C

is low,

the output data is inverted. The Q outputs can be

placed in the high-impedance state by taking the

output-enable (OE

) input high. OE does not affect

the internal operation of the register. Old data can

be retained or new data can be entered while the

outputs are off.

A low level at the clear (CLR

) input resets the

internal registers low. The clear function is

asynchronous and overrides all other register

functions.

The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum

for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.

The SN54ALS996 is characterized for operation over the full military temperature range of −55°C to 125°C. The

SN74ALS996 is characterized for operation from 0°C to 70°C.

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Summary of content (19 pages)

PAGE 1
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 • • • • SN54ALS996 . . . JT PACKAGE SN74ALS996 . . .
PAGE 2
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 logic symbol† 15 OE 14 T/C 13 CLR EN4 N3 R 10 & RD EN2 9 EN CLK 1D ≥1 11 1 C1 1D 3,4 2 2D 3D 4D 5D 6D 7D 8D 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
PAGE 3
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 timing diagram (T/C = H) CLR D ÌÌ ÌÌ ÌÌ Input Data tsu Read-Back Data th tw CLK tdis ten tsu EN th† tdis ten RD tp Q Output Output Data tdis ten OE Async Clear Write Read Back † This hold time ensures that the read-back circuit will not create a conflict on the input data bus.
PAGE 4
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 recommended operating conditions SN54ALS996 VCC Supply voltage SN74ALS996 NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 All inputs VIH High-level input voltage IOH All inputs except OE, RD 2 IOL Low-level output current 0.8 0.8 Q −1 −2.6 D −0.4 −0.
PAGE 5
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK SN54ALS996 TYP† MAX TEST CONDITIONS MIN All outputs VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = − 18 mA IOH = − 0.4 mA Q VCC = 4.5 V IOH = − 1 mA IOH = − 2.6 mA VCC = 4.5 V IOL = 4 mA IOL = 8 mA 0.25 D VCC = 4.5 V IOL = 12 mA IOL = 24 mA IOL = 48 mA‡ 0.
PAGE 6
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.
PAGE 7
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V 7V S1 S1 500 Ω 1 kΩ Test Point From Output Under Test CL (see Note A) CL (see Note A) 500 Ω LOAD CIRCUIT FOR Q OUTPUTS 1 kΩ LOAD CIRCUIT FOR D OUTPUTS 3.5 V Timing Input Test Point From Output Under Test 3.5 V High-Level Pulse 1.3 V 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 0.
PAGE 8
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995 2−8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 •
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALS996DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS996DWR SOIC DW 24 2000 367.0 367.0 45.
PAGE 14
MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.
PAGE 15
MECHANICAL DATA MCFP007 – OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30° TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.