Datasheet

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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

GND

Y10

Y11

Y12

Y13

GND

Y14

Y15

Y16

Y17

Y18

GND

Y19

Y20

CLK

GND

A10

A11

A12

A13

GND

A14

A15

A16

A17

A18

GND

A19

A20

NC − No internal connection

SN74ALVC162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES129E – MARCH 1998 – REVISED OCTOBER 2004

• Member of the Texas Instruments Widebus™

Family

• Operates From 1.65 V to 3.6 V

• Max t

of 4 ns at 3.3 V

• ± 12-mA Output Drive at 3.3 V

• Output Port Has Equivalent 26- Ω Series

Resistors, So No External Resistors Are

Required

• Designed to Comply With JEDEC 168-Pin and

200-Pin SDRAM Buffered DIMM Specification

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This 20-bit universal bus driver is designed for 1.65-V

to 3.6-V V

operation.

Data flow from A to Y is controlled by the

output-enable ( OE) input. The device operates in the

transparent mode when the latch-enable ( LE) input is

low. When LE is high, the A data is latched if the

clock (CLK) input is held at a high or low logic level. If

LE is high, the A data is stored in the latch/flip-flop on

the low-to-high transition of CLK. When OE is high,

the outputs are in the high-impedance state.

The output port includes equivalent 26- Ω series

resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up

or power down, OE should be tied to V

through a

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVC162836DL

SSOP - DL ALVC162836

Tape and reel SN74ALVC162836DLR

-40 ° C to 85 ° C

TSSOP - DGG Tape and reel SN74ALVC162836DGGR ALVC162836

TVSOP - DGV Tape and reel SN74ALVC162836DGVR VC2836

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (12 pages)

PAGE 1
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES129E – MARCH 1998 – REVISED OCTOBER 2004 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 4 ns at 3.3 V ±12-mA Output Drive at 3.
PAGE 2
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.
PAGE 3
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES129E – MARCH 1998 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.
PAGE 4
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES129E – MARCH 1998 – REVISED OCTOBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V MIN MAX fclock tw tsu th (1) Setup time Hold time MIN (1) Clock frequency Pulse duration VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX MIN MAX 150 MIN 150 150 LE low (1) 3.3 3.3 3.3 CLK high or low (1) 3.3 3.3 3.
PAGE 5
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES129E – MARCH 1998 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALVC162836DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74ALVC162836DGVR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVC162836DGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74ALVC162836DGVR TVSOP DGV 56 2000 346.0 346.0 41.
PAGE 9
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 10
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 11
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 12
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.