Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting TFSOP 48

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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DL PACKAGE

(TOP VIEW)

1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1CLK

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2CLK

The outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω resistors to reduce overshoot and

SN74ALVCH162374

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES092F – JANUARY 1997 – REVISED OCTOBER 2004

• Member of the Texas Instruments Widebus™

Family

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Output Ports Have Equivalent 26- Ω Series

Resistors, So No External Resistors Are

Required

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

This 16-bit edge-triggered D-type flip-flop is designed

for 1.65-V to 3.6-V V

operation.

The SN74ALVCH162374 is particularly suitable for

implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers. It can be used as

two 8-bit flip-flops or one 16-bit flip-flop. On the

positive transition of the clock (CLK) input, the Q

outputs of the flip-flop take on the logic levels set up

at the data (D) inputs.

The output-enable ( OE) input can be used to place

the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the

high-impedance state, the outputs neither load nor

drive the bus lines significantly. The high-impedance

state and the increased drive provide the capability to

drive bus lines without need for interface or pullup

components. OE does not affect internal operations

of the flip-flop. Old data can be retained or new data

can be entered while the outputs are in the

high-impedance state.

undershoot.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVCH162374DL

SSOP - DL ALVCH162374

-40 ° C to 85 ° C Tape and reel SN74ALVCH162374DLR

TSSOP - DGG Tape and reel SN74ALVCH162374GR ALVCH162374

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (13 pages)

PAGE 1
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.
PAGE 2
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES092F – JANUARY 1997 – REVISED OCTOBER 2004 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state.
PAGE 3
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.
PAGE 4
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES092F – JANUARY 1997 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.
PAGE 5
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES092F – JANUARY 1997 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = -4 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.7 V 2 IOH = -12 mA 3V 2 IOL = 100 µA II(hold) MAX 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 2.3 V 0.4 2.
PAGE 6
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES092F – JANUARY 1997 – REVISED OCTOBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) (1) MIN TYP (1) fmax tpd VCC = 2.5 V ± 0.2 V VCC = 1.8 V CLK MIN VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX MIN 150 MAX 150 (1) 1 5.4 5.4 1 6.5 1 5.
PAGE 7
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES092F – JANUARY 1997 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALVCH162374DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74ALVCH162374GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH162374DLR SSOP DL 48 1000 346.0 346.0 49.0 SN74ALVCH162374GR TSSOP DGG 48 2000 346.0 346.0 41.
PAGE 11
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 12
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 13
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.