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FEATURES

DESCRIPTION

DGG OR DL PACKAGE

(TOP VIEW)

1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

1Q7

GND

1Q8

1Q9

1Q10

2Q1

2Q2

2Q3

GND

2Q4

2Q5

2Q6

2Q7

2Q8

GND

2Q9

2Q10

2OE

1LE

1D1

1D2

GND

1D3

1D4

1D5

1D6

1D7

GND

1D8

1D9

1D10

2D1

2D2

2D3

GND

2D4

2D5

2D6

2D7

2D8

GND

2D9

2D10

2LE

SN74ALVCH162841

20-BIT BUS-INTERFACE D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004

• Member of the Texas Instruments Widebus™

Family

• EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

• Output Ports Have Equivalent 26- Ω Series

Resistors, So No External Resistors Are

Required

• ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

NOTE: For tape-and-reel order entry, the DGGR package is

abbreviated to GR.

This 20-bit bus-interface D-type latch is designed for

1.65-V to 3.6-V V

operation.

The SN74ALVCH162841 features 3-state outputs

designed specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing buffer registers,

unidirectional bus drivers, and working registers.

The SN74ALVCH162841 can be used as two 10-bit

latches or one 20-bit latch. The 20-bit latch is a

transparent D-type latch. The device has noninverting

data (D) inputs and provides true data at its outputs.

While the latch-enable (1LE or 2LE) input is high, the

Q outputs of the corresponding 10-bit latch follow the

D inputs. When LE is taken low, the Q outputs are

latched at the levels set up at the D inputs.

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A buffered output-enable (1 OE or 2 OE) input can be used to place the outputs of the corresponding 10-bit latch

in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,

the outputs neither load nor drive the bus lines significantly.

OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω resistors to reduce overshoot and

undershoot.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
www.ti.
PAGE 2
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 DESCRIPTION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.
PAGE 3
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE 1 2OE 56 2LE C1 1D1 55 1D 2 28 29 C1 1Q1 2D1 42 To Nine Other Channels 15 1D 2Q1 To Nine Other Channels ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.
PAGE 4
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.
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SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = -4 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.7 V 2 IOH = -12 mA 3V 2 IOL = 100 µA II(hold) MAX 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 2.3 V 0.4 2.3 V 0.
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SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) PARAMETER tpd (1) FROM (INPUT) TO (OUTPUT) D Q LE VCC = 1.8 V TYP VCC = 2.5 V VCC = 3.3 V VCC = 2.7 V ± 0.2 V ± 0.3 V MIN MAX MIN MAX UNIT MIN MAX (1) 1 5.3 5.2 1.2 4.3 (1) 1 5.9 5.6 1 4.7 ns ten OE Q (1) 1 6.
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SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 9
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALVCH162841GR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH162841GR TSSOP DGG 56 2000 346.0 346.0 41.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
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