Datasheet

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FEATURES

XXXX

DGG OR DL PACKAGE

(TOP VIEW)

1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1LE

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2LE

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

SN74ALVCH16373

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES020I – JULY 1995 – REVISED NOVEMBER 2005

• Member of the Texas Instruments Widebus™

Family

• Operates From 1.65 V to 3.6 V

• Max t

of 3.6 ns at 3.3 V

• ± 24-mA Output Drive at 3.3 V

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 16-bit transparent D-type latch is designed for

1.65-V to 3.6-V V

operation.

The SN74ALVCH16373 is particularly suitable for

implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers. This device can

be used as two 8-bit latches or one 16-bit latch.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is taken

low, the Q outputs are latched at the levels set up at

the D inputs.

A buffered output-enable ( OE) input can be used to

place the eight outputs in either a normal logic state

(high or low logic levels) or the high-impedance state.

In the high-impedance state, the outputs neither

load nor drive the buslines significantly. The

high-impedance state and the increased drive provide

the capability to drive bus lines without need for

interface or pullup components. OE does not affect

internal operations of the latch. Old data can be

retained or new data can be entered while the

outputs are in the high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 3.6 ns at 3.3 V ±24-mA Output Drive at 3.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES020I – JULY 1995 – REVISED NOVEMBER 2005 FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE 1D1 1 2OE 48 2LE C1 47 1D 2 1Q1 24 25 C1 2D1 36 To Seven Other Channels 13 1D 2Q1 To Seven Other Channels Pin numbers shown are for the DGG and DL packages.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES020I – JULY 1995 – REVISED NOVEMBER 2005 Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V 0.65 × VCC VCC = 2.3 V to 2.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES020I – JULY 1995 – REVISED NOVEMBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA 1.65 V to 3.6 V 1.65 V IOH = –6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 IOH = –12 mA II(hold) V 3V 2.4 3V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES020I – JULY 1995 – REVISED NOVEMBER 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER D tpd LE ten OE tdis (1) VCC = 1.8 V TO (OUTPUT) OE TYP VCC = 2.5 V ± 0.2 V VCC = 2.7 V MIN MAX (1) 1 (1) 1 Q (1) Q (1) Q MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 4.5 4.3 1.1 3.6 4.9 4.6 1 3.9 1 6 5.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES020I – JULY 1995 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74ALVCH16373ZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 74ALVCH16373ZRDR BGA MI CROSTA R JUNI OR ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 SN74ALVCH16373DGGR TSSOP DGG 48 2000 330.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ALVCH16373ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 74ALVCH16373ZRDR BGA MICROSTAR JUNIOR ZRD 54 1000 333.2 345.9 28.6 SN74ALVCH16373DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ALVCH16373DLR SSOP DL 48 1000 367.0 367.0 55.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.