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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DL PACKAGE

(TOP VIEW)

PRE

SEL0

1A1

GND

1A2

1A3

1A4

1A5

1A6

GND

1A7

1A8

1A9

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2A9

SEL1

SEL2

CLK

SELEN

1B1

GND

1B2

1B3

1B4

1B5

1B6

GND

1B7

1B8

1B9

2B1

2B2

2B3

GND

2B4

2B5

2B6

2B7

2B8

GND

2B9

SEL4

SEL3

To ensure the high-impedance state during power up or power down, PRE should be tied to V

through a pullup

SN74ALVCH16409

9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER

WITH 3-STATE OUTPUTS

SCES022G – JULY 1995 – REVISED OCTOBER 2004

• Member of the Texas Instruments Widebus™

Family

• UBE™ (Universal Bus Exchanger) Allows

Synchronous Data Exchange

• Operates From 1.65 V to 3.6 V

• Max t

of 5.1 ns at 3.3 V

• ± 24-mA Output Drive at 3.3 V

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

This 9-bit, 4-port universal bus exchanger is designed

for 1.65-V to 3.6-V V

operation.

The SN74ALVCH16409 allows synchronous data

exchange between four different buses. Data flow is

controlled by the select (SEL0–SEL4) inputs. A

data-flow state is stored on the rising edge of the

clock (CLK) input if the select-enable ( SELEN) input

is low. Once a data-flow state has been established,

data is stored in the flip-flop on the rising edge of

CLK if SELEN is high.

The data-flow control logic is designed to allow

glitch-free data transmission.

When preset ( PRE) transitions high, the outputs are

disabled immediately, without waiting for a clock

pulse. To leave the high-impedance state, both PRE

and SELEN must be low, and a clock pulse must be

applied.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVCH16409DL

SSOP - DL ALVCH16409

-40 ° C to 85 ° C Tape and reel SN74ALVCH16409DLR

TSSOP - DGG Tape and reel SN74ALVCH16409DGGR ALVCH16409

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, UBE are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (11 pages)

PAGE 1
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES022G – JULY 1995 – REVISED OCTOBER 2004 FEATURES • • • • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family UBE™ (Universal Bus Exchanger) Allows Synchronous Data Exchange Operates From 1.65 V to 3.6 V Max tpd of 5.1 ns at 3.3 V ±24-mA Output Drive at 3.
PAGE 2
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.
PAGE 3
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.
PAGE 4
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES022G – JULY 1995 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX -0.5 4.6 Except I/O ports (2) -0.5 4.6 I/O ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.
PAGE 5
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES022G – JULY 1995 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA V 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 IOL = 24 mA II(hold) 1.2 IOL = 4 mA IOL = 12 mA 2.7 V 0.
PAGE 6
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES022G – JULY 1995 – REVISED OCTOBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V MIN Clock frequency tw Pulse duration, CLK high or low th (1) MAX MIN Setup time Hold time VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX (1) fclock tsu VCC = 2.5 V ± 0.2 V MIN MAX 120 MIN 120 120 (1) 4.2 4.2 3 A or B before CLK↑ (1) 1.
PAGE 7
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.
PAGE 8
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES022G – JULY 1995 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.