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FEATURES

DESCRIPTION

DGG OR DL PACKAGE

(TOP VIEW)

1OE1

1Y1

1Y2

GND

1Y3

1Y4

1Y5

1Y6

1Y7

GND

1Y8

1Y9

1Y10

2Y1

2Y2

2Y3

GND

2Y4

2Y5

2Y6

2Y7

2Y8

GND

2Y9

2Y10

2OE1

1OE2

1A1

1A2

GND

1A3

1A4

1A5

1A6

1A7

GND

1A8

1A9

1A10

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2A9

2A10

2OE2

SN74ALVCH16827

20-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES041D – JULY 1995 – REVISED SEPTEMBER 2004

• Member of the Texas Instruments Widebus™

Family

• EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

• ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

This 20-bit noninverting buffer/driver is designed for

1.65-V to 3.6-V V

operation.

The SN74ALVCH16827 is composed of two 10-bit

sections with separate output-enable signals. For

either 10-bit buffer section, the two output-enable

(1 OE1 and 1 OE2 or 2 OE1 and 2 OE2) inputs must

both be low for the corresponding Y outputs to be

active. If either output-enable input is high, the

outputs of that 10-bit buffer section are in the

high-impedance state.

To ensure the high-impedance state during power up

or power down, OE should be tied to V

through a

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.

Active bus-hold circuitry is provided to hold unused or

floating data inputs at a valid logic level.

The SN74ALVCH16827 is characterized for operation

from -40 ° C to 85 ° C.

FUNCTION TABLE

(each 10-bit section)

INPUTS

OUTPUT

OE1 OE2 A

L L L L

L L H H

H X X Z

X H X Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (14 pages)

PAGE 1
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.
PAGE 2
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.
PAGE 3
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES041D – JULY 1995 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.
PAGE 4
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES041D – JULY 1995 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IOH = -12 mA II(hold) 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 1.65 V 25 1.65 V -25 VI = 0.7 V 2.
PAGE 5
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES041D – JULY 1995 – REVISED SEPTEMBER 2004 OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd (1) Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 16 18 (1) 4 6 UNIT pF This information was not available at the time of publication.
PAGE 6
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES041D – JULY 1995 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VOL + 0.
PAGE 7
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES041D – JULY 1995 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 8
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES041D – JULY 1995 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74ALVCH16827DGGR TSSOP SN74ALVCH16827DLR SSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH16827DGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74ALVCH16827DLR SSOP DL 56 1000 346.0 346.0 49.
PAGE 12
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 13
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 14
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