Datasheet

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SN54ALVTH16240, SN74ALVTH16240

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCES138A – JULY 1998 – REVISED JANUARY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

State-of-the-Art Advanced BiCMOS

Technology (ABT)

Widebus

 Design for

2.5-V and 3.3-V Operation and Low Static

Power Dissipation

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 2.3-V to

3.6-V V

)

Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

High Drive (–24/24 mA at 2.5-V and

–32/64 mA at 3.3-V V

)

Power Off Disables Outputs, Permitting

Live Insertion

High-Impedance State During Power Up

and Power Down Prevents Driver Conflict

Use Bus Hold on Data Inputs in Place of

External Pullup/Pulldown Resistors to

Prevent the Bus From Floating

Auto3-State Eliminates Bus Current

Loading When Output Exceeds V

+ 0.5 V

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model; and Exceeds 1000 V

Using Charged-Device Model, Robotic

Method

Flow-Through Architecture Facilitates

Printed Circuit Board Layout

Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), Thin Very

Small-Outline (DGV) Packages, and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

description

The ’ALVTH16240 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V V

operation, but with

the capability to provide a TTL interface to a 5-V system environment.

These devices are designed specifically to improve both the performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented receivers and transmitters.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1OE

1Y1

1Y2

GND

1Y3

1Y4

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

4A1

4A2

GND

4A3

4A4

3OE

SN54ALVTH16240 . . . WD PACKAGE

SN74ALVTH16240 . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

Widebus is a trademark of Texas Instruments Incorporated.

Summary of content (17 pages)

PAGE 1
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 D D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus  Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High Drive (–24/24 mA at 2.5-V and –32/64 mA at 3.
PAGE 2
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 description (continued) The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide inverting outputs and symmetrical active-low output-enable (OE) inputs. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.
PAGE 3
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.
PAGE 4
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3) SN54ALVTH16240 SN74ALVTH16240 MIN MAX MIN 2.7 2.3 VCC VIH Supply voltage 2.3 High-level input voltage 1.7 VIL VI Low-level input voltage IOH High-level output current IOL ∆t/∆v TYP TYP 2.7 1.7 0 VCC 5.5 0.7 0 VCC –6 Low-level output current V V 5.
PAGE 5
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = –18 mA IOH = –100 µA 3V VCC = 2 2.3 IOH = –6 mA IOH = –8 mA VCC = 2.3 V to 2.7 V, VOL VCC = 2 2.3 3V Control inputs VCC = 2.7 V, VCC = 0 or 2.
PAGE 6
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –24 mA IOH = –32 mA VCC = 3 V to 3.6 V, VOL VCC = 3 V Control inputs Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# IEX|| 2 IOL = 100 µA IOL = 16 mA 0.
PAGE 7
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y OE Y tPHZ tPLZ SN54ALVTH16240 SN74ALVTH16240 MIN MAX MIN MAX 1 3.8 1 3.7 1 3.6 1 3.5 1 5.4 1 5.3 1 4.3 1 4.2 1 4.8 1 4.
PAGE 8
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 9
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES138A – JULY 1998 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 3V 1.5 V 0V 0V Output Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V 1.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALVTH16240DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74ALVTH16240GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74ALVTH16240VR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVTH16240DLR SSOP DL 48 1000 367.0 367.0 55.0 SN74ALVTH16240GR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ALVTH16240VR TVSOP DGV 48 2000 367.0 367.0 38.
PAGE 14
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 15
PAGE 16
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 17
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